參數(shù)資料
型號(hào): SC28L202A1B
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 微控制器/微處理器
英文描述: Dual universal asynchronous receiver/transmitter DUART
中文描述: 2 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP52
封裝: 10 X 10 MM, 2 MM HEIGHT, PLASTIC, MO-108, SOT-379-1, QFP-52
文件頁(yè)數(shù): 63/77頁(yè)
文件大?。?/td> 531K
代理商: SC28L202A1B
Philips Semiconductors
Objective specification
SC28L202
Dual UART
2000 Feb 10
57
AC CHARACTERISTICS
1,2,3
(NOMINAL 5 VOLTS)
Vcc = 5v
±
10% Ta = – 40 to +85 C unless otherwise specified
LIMITS
4
Min
Symbol
Reset timing (See Figure 3)
t
RES
Bus Timing
5
(See Figure ___)
t
*AS
A6–A0 setup time to RDN, WRN Low
t
*AH
A6–A0 hold time from RDN, WRN low
t
*CS
CEN setup time to RDN, WRN low
t
*CH
CEN Hold time from RDN. WRN Hi
t
*RW
WRN, RDN pulse width (Low time)
t
*DD
Data valid after RDN low (125 pf load) See loading table for smaller loads
t
*DA
RDN low to data bus active
6
t
*DF
Data bus floating after RDN or CEN high
t
*DI
RDN or CEN high to data bus invalid
7
t
*DS
Data bus setup time before WRN or CEN high (write cycle)
t
*DH
Data hold time after WRN high
t
*RWD
High time between read and/or write cycles
5,7
Port Timing
5
(See Figure 7)
t
*PS
Port in setup time before RDN low (Read IP ports cycle)
t
*PH
Port in hold time after RDN high
t
*PD
OP port valid after WRN or CEN high (OPR write cycle)
Interrupt Timing (See Figure 8)
INTRN (or I/O(7:3)B when used as interrupts) negated from:
Read RxFIFO (RxRDY/FFULL interrupt)
Write TxFIFO (TxRDY interrupt)
t
*IR
Reset Command (delta break change interrupt)
Stop C/T command (Counter/timer interrupt
Read IPCR (delta input port change interrupt)
Write IMR (Clear of change interrupt mask bit(s))
Clock Timing (See Figure 9)
t
*CLK
X1/CLK high or low time
f
*CLK
X1/CLK frequency (7.0 to 16.2 MHz with crystal)
f
*CTC
C/T Clk (IP2) high or low time (C/T external clock input)
f
*CTC
C/T Clk (IP2) frequency
8
t
*RX
RxC high or low time (16X)
f
*RX
RxC Frequency (16X)
RxC Frequency (1x)
8,9
t
*TX
TxC High or low time (16X)
f
*TX
TxC frequency (16X)
TxC frequency (1X)
8,9
Transmitter Timing (See Figure 12)
t
*TXD
TxD output delay from TxC low (TxC input pin)
t
*TCS
Output delay from TxC output pin low to TxD data output
Receiver Timing (See Figure 13)
t
*RXS
RxD data setup time to RxC high
t
*RXH
RxD data hold time from RxC high
68000 or Motorola bus timing (See Figure ___)
t
DCR
DACKN Low (read cycle) from X1 High
T
DCW
DACKN Low (write cycle) from X1 High
T
DAH
DACKN High from CSN or IACKN high
t
DAT
DACKN High impedance from CSN or IACKN high
t
CSC
CSN or IACKN setup time to X1 high for minimum DACKN cycle
Parameter
Typ
Max
UNIT
Reset Pulse Width
100
18
ns
10
20
0
0
15
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
15
40
0
20
0
25
0
15
17
–15
12
0
0
–20
–20
40
ns
ns
ns
60
40
40
40
40
40
40
60
60
60
60
60
60
ns
ns
ns
ns
ns
ns
30
1.0
30
0
30
0
0
30
20
14.7
20
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
50
50
3
50
3
0
40
6
60
30
ns
ns
50
50
40
40
ns
ns
15
15
8
8
8
20
20
10
10
ns
ns
ns
ns
ns
10
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SC28L202A1DGG,118 功能描述:UART 接口集成電路 3-5V 2CH UART 3MBPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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