參數(shù)資料
型號(hào): SC28L202A1B
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Dual universal asynchronous receiver/transmitter DUART
中文描述: 2 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP52
封裝: 10 X 10 MM, 2 MM HEIGHT, PLASTIC, MO-108, SOT-379-1, QFP-52
文件頁(yè)數(shù): 48/77頁(yè)
文件大?。?/td> 531K
代理商: SC28L202A1B
Philips Semiconductors
Objective specification
SC28L202
Dual UART
2000 Feb 10
42
REGISTER DESCRIPTIONS Mode Registers
MR0 Mode Register 0 MR0 is accessed by setting the MR pointer to 0 via the command register command B.
Bit 7
BIT 6
MR0 A
MR0 B
MR0 B[3:0]
are reserved
1 = Enable
BIT (5:4)
TxINT (1:0)
See table #4
BIT 3
FIFO Size
0 = 8
1 = 256
BIT 2
BAUD RATE
EXTENDED II
0 = Norma
1 = Extend II
BIT 1
TEST 2
Set to 0
BIT 0
BAUD RATE
EXTENDED 1
0 = Normal
1 = Extend
Rx WATCH
DOG
0 = Disable
RxINT BIT 2
See Tables in
MR0 description
MR0[7] This bit controls the receiver watchdog timer. 0 = disable,
1 = enable. When enabled, the watch dog timer will generate a
receiver interrupt if the receiver FIFO has not been accessed within
64 bit times of the receiver 1X clock. This is used to alert the control
processor that data is in the RxFIFO that has not been read. This
situation may occur when the byte count of the last part of a
message is not large enough to generate an interrupt. This control
bit is duplicated WCXER(7:6)
MR0[6] – Bit 2 of receiver FIFO interrupt level. This bit along with Bit
6 of MR1 sets the fill level of the 8 byte FIFO that generates the
receiver interrupt.
MR0[6] MR1[6] Note that this control is split between MR0 and MR1.
This is for backward compatibility to the SC2692 and SCN2681.
Table 9. Receiver FIFO Interrupt Fill Level
MR0(3)=0
MR0[6] MR1[6]
Interrupt Condition
00
1 or more bytes in FIFO (Rx RDY)
01
3 or more bytes in FIFO
10
6 or more bytes in FIFO
11
8 bytes in FIFO (Rx FULL)
Table 10. Receiver FIFO Interrupt Fill Level
MR0(3)=1
MR0[6] MR1[6]
Interrupt Condition
00
1 or more bytes in FIFO (Rx RDY)
01
128 or more bytes in FIFO
10
192 or more bytes in FIFO
11
256 bytes in FIFO (Rx FULL)
For the receiver these bits control the number of FIFO positions
empty when the receiver will attempt to interrupt. After the reset the
receiver FIFO is empty. The default setting of these bits cause the
receiver to attempt to interrupt when it has one or more bytes in it.
MR0[5:4] – Tx interrupt fill level.
Table 11. Transmitter FIFO Interrupt Fill Level
MR0(3)=0
MR0[5:4]
Interrupt Condition
00
8 bytes empty (Tx EMPTY)
01
4 or more bytes empty
10
6 or more bytes empty
11
1 or more bytes empty (Tx RDY)
Table 12. Transmitter FIFO Interrupt Fill Level
MR0(3)=1
MR0[5:4]
Interrupt Condition
00
256 bytes empty (Tx EMPTY)
01
128 or more bytes empty
10
192 or more bytes empty
11
1 or more bytes empty (Tx RDY)
For the transmitter these bits control the number of FIFO positions
empty when the receiver will attempt to interrupt. After the reset the
transmit FIFO has 8 bytes empty. It will then attempt to interrupt as
soon as the transmitter is enabled. The default setting of the MR0
bits (00) condition the transmitter to attempt to interrupt only when it
is completely empty. As soon as one byte is loaded, it is no longer
empty and hence will withdraw its interrupt request.
MR0[3] – FIFO Size
MR0[2:0] – These bits are used to select one of the six–baud rate
groups.
See Table 13 for the group organization.
000 Normal mode
001 Extended mode I
100 Extended mode II
Other combinations of MR2[2:0] should not be used
NOTE
: MR0[3:0] are not used in channel B and should be set to 0.
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