參數(shù)資料
型號： SC28L202A1B
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Dual universal asynchronous receiver/transmitter DUART
中文描述： 2 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PQFP52
封裝： 10 X 10 MM, 2 MM HEIGHT, PLASTIC, MO-108, SOT-379-1, QFP-52
文件頁數(shù)： 54/77頁
文件大?。?/td> 531K
代理商： SC28L202A1B
Philips Semiconductors
Objective specification
SC28L202
Dual UART
2000 Feb 10
48
ISR – Interrupt Status Register
This register provides the status of all potential interrupt sources.
The contents of this register are masked by the Interrupt Mask
Register (IMR). If a bit in the ISR is a ‘1’ and the corresponding bit in
the IMR is also a ‘1’ then INTRN output will be asserted (Low). If the
corresponding bit in the IMR is a zero the state of the bit in the ISR
has no effect on the INTRN output. Note that the IMR does not mask
the reading of the ISR – the true status will be provided regardless
of the contents of the IMR. The contents of this register are
initialized to H‘00’ when the DUART is reset.
ISR
Bit 7
INPUT
PORT
CHANGE
0=not enabled
1=enabled
BIT 6
DELTA
Break B
BIT 5
RxRDY/
FFULL B
BIT 4
TxRDY B
BIT 3
Counter
Ready
BIT 2
Delta
Break A
BIT 1
RxRDY/
FFULL A
BIT 0
TxRDY A
0=not enabled
1=enabled
0=not
enabled
1=enabled
0=not enabled
1=enabled
0=not enabled
1=enabled
0=not enabled
1=enabled
0=not enabled
1=enabled
0=not enabled
1=enabled
ISR[7] – Input Port Change Status
This bit is a ‘1’ when a change–of–state has occurred at the
I/O(3:0)A or B inputs and that event has been selected to cause an
interrupt by the programming of ACR[3:0]. The bit is cleared when
the CPU reads the IPCR.
ISR[6] – Channel B Change In Break
This bit, when set, indicates that the Channel B receiver has
detected the beginning or the end of a received break. It is reset
when the CPU issues a Channel B ‘reset break change interrupt’
command.
ISR[5] – Rx B Interrupt
This bit indicates that the channel B receiver is interrupting
according to the fill level programmed by the MR0 and MR1
registers. This bit has a different meaning than the receiver
ready/full bit in the status register.
ISR[4] – Tx B Interrupt
This bit indicates that the channel B transmitter is interrupting
according to the interrupt level programmed in the MR0[5:4] bits.
This bit has a different meaning than the Tx RDY bit in the status
register.
ISR[3] – Counter Ready.
In the counter mode, this bit is set when the counter reaches
terminal count and is reset when the counter is stopped by a stop
counter command.
In the timer mode, this bit is set once each cycle of the generated
square wave (every other time that the counter/timer reaches zero
count). The bit is reset by a stop counter command. The command,
however, does not stop the counter/timer.
ISR[2] – Channel A Change in Break
This bit, when set, indicates that the Channel A receiver has
detected the beginning or the end of a received break. It is reset
when the CPU issues a Channel A ‘reset break change interrupt’
command.
ISR[1] – Rx A Interrupt
This bit indicates that the channel A receiver is interrupting
according to the fill level programmed by the MR0 and MR1
registers. This bit has a different meaning than the receiver
ready/full bit in the status register.
ISR[0] – Tx A Interrupt
This bit indicates that the channel A transmitter is interrupting
according to the interrupt level programmed in the MR0[5:4] bits.
This bit has a different meaning than the Tx RDY bit in the status
register.
IMR – Interrupt Mask Register
The programming of this register selects which bits in the ISR
causes an interrupt output. If a bit in the ISR is a ‘1’ and the
corresponding bit in the IMR is also a ‘1’ the INTRN output will be
asserted. If the corresponding bit in the IMR is a zero, the state of
the bit in the ISR has no effect on the INTRN output. Note that the
IMR does not mask the programmable interrupt outputs I/O3 B–I/O7
B or the reading of the ISR.
IMR
Bit 7
INPUT PORT
CHANGE
0=not
enabled
1=enabled
BIT 6
Delta
Break B
0=not
enabled
1=enabled
BIT 5
RxRDY/
FFULL B
0=not
enabled
1=enabled
BIT 4
TxRDY B
BIT 3
Counter
Ready
0=not
enabled
1=enabled
BIT 2
Delta
Break A
0=not
enabled
1=enabled
BIT 1
RxRDY/
FFULL A
0=not
enabled
1=enabled
BIT 0
TxRDY A
0=not
enabled
1=enabled
0=not
enabled
1=enabled
CTPU Counter Timer Preset Upper (Counter/Timer 0)
CPTU
Bit 7
The upper eight (8) bits for the 16 bit counter timer preset register
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CTPL Counter –Timer Preset Lower
(Counter/Timer 0)
CTPL
Bit 7
The lower eight (8) bits for the 16 bit counter timer preset register
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CTVU Counter Timer Value Upper (Counter/Timer 0)
CPVL
Bit 7
The lower eight (8) bits for the 16 bit counter timer value
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
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SC28L202A1D 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual universal asynchronous receiver/transmitter DUART
SC28L202A1DGG 功能描述:UART 接口集成電路 3-5V 2CH UART 3MBPS 256B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L202A1DGG,112 功能描述:UART 接口集成電路 3-5V 2CH UART 3MBPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L202A1DGG,118 功能描述:UART 接口集成電路 3-5V 2CH UART 3MBPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L202A1DGG,129 功能描述:UART 接口集成電路 3-5V 2CH UART 3MBPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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