參數(shù)資料
型號(hào): SC28C198A1A
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 微控制器/微處理器
英文描述: Octal UART for 3.3V and 5V supply voltage
中文描述: 8 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC84
封裝: PLASTIC, MO-047AF, SOT-189-3, LCC-84
文件頁(yè)數(shù): 6/56頁(yè)
文件大?。?/td> 345K
代理商: SC28C198A1A
Philips Semiconductors
Product specification
SC28L198
Octal UART for 3.3V and 5V supply voltage
1999 Jan 14
6
SClk
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CEN
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fall or rise time. The user must be aware of the possible generation of ringing and reflections on improperly terminated interconnections. See
previous note on Sclk noise under pin assignments.
Host system clock. Used to time operations in the Host Interface and clock internal logic. Must be greater
than twice the frequency of highest X1, Counter/Timer, TxC (1x) or RxC (1x) input frequency.
Chip select: Active low. When asserted, allows I/O access to OCTART registers by host CPU. W_RN signal
indicates direction. (
Must not be active in IACKN cycle
)
8–bit bi–directional data bus. Carries command and status information between 28L198 and the host CPU.
Used to convey parallel data for serial I/O between the host CPU and the 28L198
When low, indicates a read cycle. 0 = Read; 1 = Write
Data Acknowledge: Active low. When asserted, it signals that the last transfer of the D lines is complete.
rupt(s). Open drain.
Interrupt Acknowledge: Active low. When asserted, indicates that the host CPU has initiated an interrupt ac-
Receive Data: Serial inputs to the 8 UARTs
Input/Output 0: Multi–use input or output pin for the UART.
Input/Output 1: Multi–use input or output pin for the UART.
Global general purpose inputs, available to any/all channels.
Global general purpose outputs, available from any channel.
Master reset: Active Low. Must be asserted at power up and may be asserted at other times to reset and re-
Crystal 1 or Communication Clock: This pin may be connected to one side of a 2–8 MHz crystal. It may alter-
natively be driven by an external clock in this frequency range. Standard frequency = 3.6864 MHz
Crystal 2: If a crystal is used, this is the connection to the second terminal. If a clock signal drives X1, this pin
8 pins total 6 pins for Vss, 2 pins for Vcc
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DACKN
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IACKN
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I/O0(a–h)
I/O1(a–h)
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0
RESETN
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I/O
I/O
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W_RN
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IRQN
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X1/CCLK
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Power Supplies
X2
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ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
TA
2
4
PD
PD
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1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
the functional operation of the device at these or any other conditions above those indicated in the Operation Section of this specification is
not implied.
2. For operating at elevated temperatures, the device must be derated based on +150C maximum junction temperature.
3. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating
supply range.
4. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge.
PARAMETER
RATING
UNIT
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See Note 3
3.78
2.08
oC
W
W
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