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參數(shù)資料
| 型號： | SC26L198C1A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Octal UART with TTL compatibility at 3.3V and 5V supply voltages |
| 中文描述： | 8 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 40/49頁 |
| 文件大?。?/td> | 358K |
| 代理商： | SC26L198C1A |
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Philips Semiconductors
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
1995 May 1
375
AC ELECTRICAL CHARACTERISTICS (26C198 and 68C198)
(Continued)
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SYMBOL
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FIGURE
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PARAMETER
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X1 L / H
X1 Low / High time
T/RFx1
X1 Rise / Fall time
TC/TO
Delay C/T clock external to output pin
DACKN TIMING
4
I/O PORT External Clock
Tgpirtx
GPI to Rx/Tx clock out
GPOtdd
GPO valid after write to GPOR
UNIT
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20
10/10
ns
ns
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ns
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60
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TBD
ns
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1. The ASYNC pulse width low must include 4 rising edges plus the setup & hold times. For those applications where the control processor
has no knowledge of the Sclk period, this will imply a CEN period of 5 Sclk rising edges.
2. Production test will use rise and fall time less than 7ns. Specified rise and fall times are guaranteed by design.
3. Sclk is required for proper bus timing. Sclk must always be faster than twice the fastest 1X data clock.
4. The meaning of DACKN is that data will be valid before the end of the C4 time.
5. All voltage measurements are relative to gnd. Input and output levels are those shown in “DC Electrical Specifications”. For testing, inputs
switch between 0.2 and 2.8V; outputs are measured between 0.8 and 2.0V.
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TBD
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ns
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相關(guān)PDF資料 |
PDF描述 |
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| SC26C198 | Octal UART with TTL compatibility at 3.3V and 5V supply voltages |
| SC26C198A1A | Octal UART with TTL compatibility at 3.3V and 5V supply voltages |
| SC26C198C1A | Octal UART with TTL compatibility at 3.3V and 5V supply voltages |
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| SC68C198A1A | Octal UART with TTL compatibility at 3.3V and 5V supply voltages |
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