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| 型號： | SC26L198C1A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Octal UART with TTL compatibility at 3.3V and 5V supply voltages |
| 中文描述： | 8 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 17/49頁 |
| 文件大?。?/td> | 358K |
| 代理商： | SC26L198C1A |
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Philips Semiconductors
Product specification
SC26C198 SC68C198
SC26L198 SC68L198
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
1995 May 1
352
* If these bits are not 0 the characters will be stripped regardless of
bits (3:2) or (1:0)
MR0[7:6] –
Control the handling of recognized Xon/Xoff or Address
characters. If set, the character codes are placed on the RxFIFO
along with their status bits just as ordinary characters are. If the
character is not pushed onto the RxFIFO, its received status will be
lost unless the receiver is operating in the block error mode, see
MR1[5] and the general discussion on receiver error handling.
Interrupt processing is not effected by the setting of these bits. See
Character recognition section.
MR0[5:4] –
Controls the fill level at which a transmitter begins to
present its interrupt number to the interrupt arbitration logic. Use of
a low fill level minimizes the number of interrupts generated and
maximizes the number of transmit characters per interrupt cycle. It
also increases the probability that the transmitter will go idle for lack
of characters in the TxFIFO.
MR0[3:2] –
Controls the Xon/Xoff processing logic. Auto
Transmitter flow control allows the gating of Transmitter activity by
Xon/Xoff characters received by the Channel’s receiver. Auto
character when the RxFIFO has loaded to a depth of 12 characters.
Draining the RxFIFO to a level of 8 or less causes the Transmitter to
emit an Xon character. All transmissions require no host
involvement. A setting other than b’00 in this field precludes the use
of the command register to transmit Xon/Xoff characters.
Note: Interrupt generation in Xon/Xoff processing is controlled by the
IMR (Interrupt Mask Register) of the individual channels. The
interrupt may be cleared by a read of the XISR, the Xon/Xoff
Interrupt Status Register. Receipt of a flow control character will
always generate an interrupt if the IMR is so programmed. The
MR0[3:2] bits have effect on the automatic aspects of flow control
only, not the interrupt generation.
MR0[1:0] –
This field controls the operation of the Address
recognition logic. If the device is not operating in the special or
“wake–up” mode, this hardware may be used as a general purpose
character detector by choosing any combination except b’00.
Interrupt generation is controlled by the channel IMR. The interrupt
may be cleared by a read of the XISR, the Xon/Xoff Interrupt Status
Register. See further description in the section on the Wake Up
Control
0 – off
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Character
00 – 5
10 – 7
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0 – ISR unmasked
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0 = Character
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00 – With Parity
10 – No parity
character at. the bottom of the FIFO. In the block mode, the status
provided in the SR for these bits is the accumulation (logical OR) of
the status for all characters coming to the top of the FIFO, since the
last reset error command was issued.
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0 = Even
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This bit controls the deactivation of the RTSN output (I/O2) by the
receiver. This output is asserted and negated by commands applied
via the command register. MR1[7] = 1 causes RTSN to be
automatically negated upon receipt of a valid start bit if the receiver
FIFO is full or greater. RTSN is reasserted when an the FIFO fill
level falls below full. This constitutes a change from previous
members of Philips (Signets)’ UART families where the RTSN
function triggered on FIFO full. This behavior caused problems with
PC UARTs that could not stop transmission at the proper time. .
The RTSN feature can be used to prevent overrun in the receiver, by
using the RTSN output signal, to control the CTSN input of the
transmitting device.
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MR1[6]: Interrupt Status Masking
This bit controls the readout mode of the Interrupt Status Register,
ISR. If set, the ISR reads the current status masked by the IMR, i.e.
only interrupt sources enabled in the IMR can ever show a ’1’ in the
ISR. If cleared, the ISR shows the current status of the interrupt
source without regard to the Interrupt Mask setting.
MR1[5]: Error Mode Select
This bit selects the operating mode of the three FIFOed status bits
(FE, PE, received break). In the character mode, status is provided
MR1[4:3]: Parity Mode Select
If ’with parity’ or ’force parity’ is selected, a parity bit is added to the
transmitted character and the receiver performs a parity check on
incoming data. MR1[4:3] = 11 selects the channel to operate in the
special wake up mode.
MR1[2]: Parity Type Select
This bit sets the parity type (odd or even) if the ’with parity’ mode is
programmed by MR1[4:3], and the polarity of the forced parity bit if
the ’force parity’ mode is programmed. It has no effect if the ’no
parity’ mode is programmed. In the special ’wake up’ mode, it
selects the polarity of the A/D bit. The parity bit is used to an
address or data byte in the ’wake up’ mode.
MR1[1:0]: Bits per Character Select
This field selects the number of data bits per character to be
transmitted and received. This number does
not
include the start,
parity, or stop bits.
Table 5. MR2 – Mode Register 2
01 = Auto echo
11 = Remote loop
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1 = Yes
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01 = Half Full
11 = Full
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01 = 1.5
11 = 9/16
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1 = Yes
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