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60
Revision 3.0
G
Signal Definitions
(Continued)
SETRES
P2
B15
I
Set Resistor.
This signal sets the current
level for the RED/GREEN/BLUE analog out-
puts. Typically, a 464
, 1% resistor is con-
nected between this ball and AV
SSCRT
.
---
On-Chip RAMDAC
RED
K1
B12
O
Analog Red, Green and Blue
---
GREEN
M3
A14
---
BLUE
N2
A15
---
TFT (External DAC) Interface
TFTDCK
A22
AA1
O
TFT Clock.
Clock to external CRT DACs or
TFT.
IDE_RST#
J4
A10
GPIO17+ IOCS0#
TFTDE
C16
P2
O
TFT Data Enable.
Can be used as blank sig-
nal to external CRT DACs.
IDE_CS1#
U3
B18
ACK#+FPCICLK
FP_VDD_ON
B23
AB1
O
TFT Power Control.
Used to enable power
to the Flat Panel display, with power
sequence timing.
IDE_DATA4
AL16
V30
GXCLK+TEST3
TFTD[17:0]
See
Table2-3
on page
32.
See
Table2-5
on page
47.
O
Digital RGB Data to TFT.
TFTD[5:0] - Connect to BLUE TFT inputs.
TFTD[11:6] - Connect to GREEN TFT inputs.
TFTD[17:12] - Connect to RED TFT inputs.
The TFT interface is
muxed with the IDE
interface or the Par-
allel Port. See Table
2-7 on page 52 and
Table 2-8 on page
54 for details.
2.4.5
ACCESS.bus Interface Signals
Signal Name
Ball No.
Type
Description
Mux
EBGA
TEPBGA
AB1C
AJ13
N31
I/O
ACCESS.bus 1 Serial Clock.
This is the
serial clock for the interface.
Note:
If selected as AB1C function but not
used, tie AB1C high.
GPIO20+DOCCS#
AB1D
AL12
N30
I/O
ACCESS.bus 1 Serial Data.
This is the bidi-
rectional serial data signal for the interface.
Note:
If AB1D function is selected but not
used, tie AB1D high.
GPIO1+IOCS1#
AB2C
AJ12
N29
I/O
ACCESS.bus 2 Serial Clock.
This is the
serial clock for the interface.
Note:
If AB2C function is selected but not
used, tie AB2C high.
GPIO12
2.4.4
CRT/TFT Interface Signals (Continued)
Signal Name
Ball No.
Type
Description
Mux
EBGA
TEPBGA