www.national.com
40
Revision 3.0
G
Signal Definitions
(Continued)
D13
V
SS
GND
---
---
---
D14
V
IO
PWR
---
---
---
D15
AV
CCCRT
PWR
---
---
---
D16
VREF
I/O
WIRE
AV
C-
CCRT
---
D17
6, 2
PE
I
(PU
22.5
PD
22.5
)
IN
T
V
IO
PMR[23]
3
= 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
(PU/PD under soft-
ware control.)
TFTD14
O
O
1/4
PMR[23]
3
= 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
F_C/BE2#
O
O
1/4
PMR[23]
3
= 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
D18
V
IO
PWR
---
---
---
D19
V
SS
GND
---
---
---
D20
6, 2
PD2
I/O
IN
T
,
O
14/14
V
IO
PMR[23]
3
= 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
TFTD8
O
O
1/4
PMR[23]
3
= 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
F_AD2
O
O
14/14
PMR[23]
3
= 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
D21
6, 2
ERR#
I
IN
T
,
O
1/4
V
IO
PMR[23]
3
= 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
TFTD4
O
O
1/4
PMR[23]
3
= 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
F_C/BE0#
O
O
1/4
PMR[23]
3
= 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
D22
6, 2
AFD#/DSTRB#
O
O
14/14
V
IO
PMR[23]
3
= 0 and
(PMR[27] = 0 and
FPCI_MON = 0)
TFTD2
O
O
1/4
PMR[23]
3
= 1 and
(PMR[27] = 0 and
FPCI_MON = 0)
INTR_O
O
O
14/14
PMR[23]
3
= 0 and
(PMR[27] = 1 or
FPCI_MON = 1)
D23
V
IO
PWR
---
---
---
D24
NC
---
---
---
---
D25
V
SS
GND
---
---
---
D26
INTA#
I
(PU
22.5
)
IN
PCI
V
IO
---
D27
AV
CCUSB
PWR
---
---
---
D28
GPIO6
I/O
(PU
22.5
)
IN
TS
,
O
1/4
V
IO
PMR[18] = 0 and
PMR[8] = 0
DTR2#/BOUT2
O
(PU
22.5
)
O
1/4
PMR[18] = 1 and
PMR[8] = 0
IDE_IOR1#
O
(PU
22.5
)
O
1/4
PMR[18] = 0 and
PMR[8] = 1
SDTEST5
O
(PU
22.5
)
O
2/5
PMR[18] = 1 and
PMR[8] = 1
Ball
No.
Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail
Configuration
D29
SOUT2
O
O
8/8
V
IO
---
CLKSEL2
I
(PD
100
)
IN
STRP
Strap (See Table 2-
6 on page 51.)
D30
TDP
I/O
Diode
---
---
D31
TDN
I/O
WIRE
V
IO
---
E1
AD16
I/O
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A16
O
O
PCI
E2
AD19
I/O
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A19
O
O
PCI
E3
AD18
I/O
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A18
O
O
PCI
E4
DEVSEL#
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
BHE#
O
O
PCI
E28
SIN2
I
IN
TS
V
IO
PMR[28] = 0
SDTEST3
O
O
2/5
PMR[28] = 1
E29
TRST#
I
(PU
22.5
)
IN
PCI
V
IO
---
E30
TDO
O
O
PCI
V
IO
---
E31
TCK
I
(PU
22.5
)
IN
PCI
V
IO
---
F1
TRDY#
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
D13
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
F2
IRDY#
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
D14
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
F3
C/BE2#
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
D10
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
F4
AD17
I/O
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
A17
O
O
PCI
F28
TMS
I
(PU
22.5
)
IN
PCI
V
IO
---
F29
TDI
I
(PU
22.5
)
IN
PCI
V
IO
---
F30
GTEST
I
(PD
22.5
)
IN
T
V
IO
---
F31
VPCKIN
I
IN
T
V
IO
---
G1
STOP#
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
V
IO
Cycle Multiplexed
D15
I/O
(PU
22.5
)
IN
PCI
,
O
PCI
G2
V
SS
GND
---
---
---
G3
V
IO
PWR
---
---
---
G4
V
SS
GND
---
---
---
Ball
No.
Signal Name
I/O
(PU/PD)
Buffer
1
Type
Power
Rail
Configuration
Table 2-4.
481-TEPBGA Ball Assignment - Sorted by Ball Number (Continued)