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Revision 3.0
G
Core Logic Module
(Continued)
Table 5-21. F2BAR4: IDE Controller Support Registers Summary
F2BAR4+
I/O Offset
Width
(Bits)
Type
Name
Reset
Value
Reference
(Table 5-36)
00h
01h
02h
03h
04h-07h
08h
09h
0Ah
0Bh
0Ch-0Fh
8
---
8
---
32
8
---
8
---
32
R/W
---
R/W
---
R/W
R/W
---
R/W
---
R/W
IDE Bus Master 0 Command Register — Primary
Not Used
IDE Bus Master 0 Status Register — Primary
Not Used
IDE Bus Master 0 PRD Table Address — Primary
IDE Bus Master 1 Command Register — Secondary
Not Used
IDE Bus Master 1 Status Register — Secondary
Not Used
IDE Bus Master 1 PRD Table Address — Secondary
00h
---
00h
---
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00000000h
00h
---
00h
---
00000000h
Table 5-22. F3: PCI Header Registers for XpressAUDIO Support Summary
F3 Index
Width
(Bits)
Type
Name
Reset
Value
Reference
(Table 5-37)
00h-01h
02h-03h
04h-05h
06h-07h
08h
09h-0Bh
0Ch
0Dh
0Eh
0Fh
10h-13h
16
16
16
16
8
24
8
8
8
8
32
RO
RO
R/W
RO
RO
RO
RO
RO
RO
RO
R/W
Vendor Identification Register
Device Identification Register
PCI Command Register
PCI Status Register
Device Revision ID Register
PCI Class Code Register
PCI Cache Line Size Register
PCI Latency Timer Register
PCI Header Type Register
PCI BIST Register
Base Address Register 0 (F3BAR0) — Sets the base address for
the memory mapped VSA audio interface control register block
(summarized in Table 5-23).
Reserved
Subsystem Vendor ID
Subsystem ID
Reserved
100Bh
0503h
0000h
0280h
00h
040100h
00h
00h
00h
00h
00000000h
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14h-2Bh
2Ch-2Dh
2Eh-2Fh
30h-FFh
---
16
16
---
---
RO
RO
---
00h
100Bh
0503h
00h
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