參數(shù)資料
型號: SC16IS762IBS,128
廠商: NXP Semiconductors
文件頁數(shù): 33/60頁
文件大小: 0K
描述: IC DUAL UART 64BYTE 32HVQFN
標(biāo)準(zhǔn)包裝: 1,500
特點: 低電流
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.5V, 3.3V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-HVQFN(5x5)
包裝: 帶卷 (TR)
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
其它名稱: 935279293128
SC16IS762IBS-F
SC16IS762IBS-F-ND
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
39 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
10.3 Addressing
Before any data is transmitted or received, the master must send the address of the
receiver via the SDA line. The first byte after the START condition carries the address of
the slave device and the read/write bit. Table 32 shows how the SC16IS752/SC16IS762’s
address can be selected by using A1 and A0 pins. For example, if these 2 pins are
connected to VDD, then the SC16IS752/SC16IS762’s address is set to 0x90, and the
master communicates with it through this address.
[1]
X = logic 0 for write cycle; X = logic 1 for read cycle.
10.4 Use of subaddresses
When a master communicates with the SC16IS752/SC16IS762 it must send a
subaddress in the byte following the slave address byte. This subaddress is the internal
address of the word the master wants to access for a single byte transfer, or the beginning
of a sequence of locations for a multi-byte transfer. A subaddress is an 8-bit byte. Unlike
the device address, it does not contain a direction (R/W) bit, and like any byte transferred
on the bus it must be followed by an acknowledge.
A register write cycle is shown in Figure 18. The START is followed by a slave address
byte with the direction bit set to ‘write’, a subaddress byte, a number of data bytes, and a
STOP signal. The subaddress indicates which register the master wants to access, and
the data bytes which follow will be written one after the other to the subaddress location.
Table 33 and Table 34 show the bits’ presentation at the subaddress byte for I2C-bus and
SPI interfaces. Bit 0 is not used, bits 2:1 select the channel, bits 6:3 select one of the
UART internal registers. Bit 7 is not used with the I2C-bus interface, but it is used by the
SPI interface to indicate a read or a write operation.
Table 32.
SC16IS752/SC16IS762 address map
A1
A0
SC16IS752/SC16IS762 I2C address (hex)[1]
VDD
0x90 (1001 000X)
VDD
VSS
0x92 (1001 001X)
VDD
SCL
0x94 (1001 010X)
VDD
SDA
0x96 (1001 011X)
VSS
VDD
0x98 (1001 100X)
VSS
0x9A (1001 101X)
VSS
SCL
0x9C (1001 110X)
VSS
SDA
0x9E (1001 111X)
SCL
VDD
0xA0 (1010 000X)
SCL
VSS
0xA2 (1010 001X)
SCL
0xA4 (1010 010X)
SCL
SDA
0xA6 (1010 011X)
SDA
VDD
0xA8 (1010 100X)
SDA
VSS
0xAA (1010 101X)
SDA
SCL
0xAC (1010 110X)
SDA
0xAE (1010 111X)
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