參數(shù)資料
型號: SC16IS762IBS,128
廠商: NXP Semiconductors
文件頁數(shù): 26/60頁
文件大?。?/td> 0K
描述: IC DUAL UART 64BYTE 32HVQFN
標準包裝: 1,500
特點: 低電流
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.5V, 3.3V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應商設備封裝: 32-HVQFN(5x5)
包裝: 帶卷 (TR)
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
其它名稱: 935279293128
SC16IS762IBS-F
SC16IS762IBS-F-ND
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
32 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.19 Extra Features Control Register (EFCR)
[1]
For SC16IS762 only.
8.20 Division registers (DLL, DLH)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLH stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
Note that DLL and DLH can only be written to before Sleep mode is enabled (before
IER[4] is set).
Table 30.
Extra Features Control Register bits description
Bit
Symbol
Description
7
IRDA MODE
IrDA mode.
0 = IrDA SIR, 316 pulse ratio, data rate up to 115.2 kbit/s
1 = IrDA SIR, 14 pulse ratio, data rate up to 1.152 Mbit/s[1]
6-
reserved
5
RTSINVER
Invert RTS signal in RS-485 mode.
0: RTS = 0 during transmission and RTS = 1 during reception
1: RTS = 1 during transmission and RTS = 0 during reception
4
RTSCON
Enable the transmitter to control the RTS pin.
0: transmitter does not control RTS pin
1: transmitter controls RTS pin
3-
reserved
2
TXDISABLE
Disable transmitter. UART does not send serial data out on the
transmit pin, but the transmit FIFO will continue to receive data from
host until full. Any data in the TSR will be sent out before the
transmitter goes into disable state.
0: transmitter is enabled
1: transmitter is disabled
1
RXDISABLE
Disable receiver. UART will stop receiving data immediately once this
bit is set to 1, and any data in the TSR will be sent to the receive FIFO.
User is advised not to set this bit during receiving.
0: receiver is enabled
1: receiver is disabled
0
9-BIT MODE
Enable 9-bit or Multidrop mode (RS-485).
0: normal RS-232 mode
1: enables RS-485 mode
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