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參數(shù)資料
| 型號(hào)： | SC16C852VIET,157 |
| 廠商： | NXP Semiconductors |
| 文件頁(yè)數(shù)： | 53/55頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC UART DUAL W/FIFO 36TFBGA |
| 產(chǎn)品培訓(xùn)模塊： | Stand-Alone UARTs |
| 標(biāo)準(zhǔn)包裝： | 2,450 |
| 特點(diǎn)： | 可編程 |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 128 字節(jié) |
| 規(guī)程： | RS485 |
| 電源電壓： | 2.5V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 36-TFBGA |
| 供應(yīng)商設(shè)備封裝： | 36-TFBGA（3.5x3.5） |
| 包裝： | 托盤(pán) |
| 其它名稱(chēng)： | 568-4019 935282518157 SC16C852VIET SC16C852VIET-ND |
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SC16C852V
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 21 January 2011
7 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
INTA
D5
30
O
Channel A interrupt output. The output state is defined by the user through
the software setting of MCR[3]. INTA is set to the active mode when MCR[3] is
set to a logic 1. INTA is set to the 3-state mode when MCR[3] is set to a logic 0.
See Table 21.
INTB
D6
29
O
Channel B interrupt output. The output state is defined by the user through
the software setting of MCR[3]. INTB is set to the active mode when MCR[3] is
set to a logic 1. INTB is set to the 3-state mode when MCR[3] is set to a logic 0.
See Table 21.
IOR
F4
19
I
Read strobe (active LOW). A HIGH to LOW transition on this signal starts the
read cycle. The SC16C852V reads a byte from the internal register and puts
the byte on the data bus for the host to retrieve.
IOW
E3
15
I
Write strobe (active LOW). A HIGH to LOW transition on this signal starts the
write cycle, and a LOW to HIGH transition transfers the data on the data bus to
the internal register.
LLA
E6
28
I
Latch Lower Address (active LOW). A logic LOW on this pin puts the VLIO
interface in the address phase of the transaction, where the lower 8 bits of the
VLIO (specifying the UART register and the channel address) are loaded into
the address latch of the device through the AD7 to AD0 bus. A logic HIGH puts
the VLIO interface in the data phase where data can are transferred between
the host and the UART.
LOWPWR F1
12
I
Low Power. When asserted (active HIGH), the device immediately goes into
low power mode. The oscillator is shut-off and some host interface pins are
isolated from the host’s bus to reduce power consumption. The device only
returns to normal mode when the LOWPWR pin is de-asserted. On the
negative edge of a de-asserting LOWPWR signal, the device is automatically
reset and all registers return to their default reset states. This pin has an
internal pull-down resistor, therefore, it can be left unconnected.
n.c.
-
11, 24, 25,
26, 27, 37
-
not connected
OP2A
-32
O
Output 2 (user-defined). This function is associated with individual channels,
A through B. The state at these pin(s) are defined by the user and through
MCR register bit 3. INTA, INTB are set to the active mode and OP2A/OP2B to
logic 0 when MCR[3] is set to a logic 1. INTA, INTB are set to the 3-state mode
and OP2A/OP2B to a logic 1 when MCR[3] is set to a logic 0 (see Table 20
“Modem Control Register bits description”, bit 3). Since these bits control both
the INTA, INTB operation and OP2A/OP2B outputs, only one function should
be used at one time, interrupt or OP function.
OP2B
-9
O
RESET
B5
36
I
Master reset (active LOW). A reset pulse will reset the internal registers and
all the outputs. The SC16C852V transmitter outputs and receiver inputs will be
disabled during reset time. (See Section 7.23 “SC16C852V external reset
condition and software reset” for initialization details.)
RIA
A4
41
I
Ring Indicator (active LOW). These inputs are associated with individual
UART channels, A through B. A logic 0 on this pin indicates the modem has
received a ringing signal from the telephone line. A logic 1 transition on this
input pin will generate an interrupt.
RIB
F5
21
I
RTSA
C6
33
O
Request to Send (active LOW). These outputs are associated with individual
UART channels, A through B. A logic 0 on the RTS pin indicates the transmitter
has data ready and waiting to send. Writing a logic 1 in the modem control
register MCR[1] will set this pin to a logic 0, indicating data is available. After a
reset this pin will be set to a logic 1.
RTSB
E5
22
O
Table 2.
Pin description …continued
Symbol
Pin
Type Description
TFBGA36
HVQFN48
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C852VIET-G | 功能描述:UART 接口集成電路 1.8V 2CH UART 128B FIFO 5MBPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C852VIET-S | 功能描述:UART 接口集成電路 1.8V 2CH UART 128B FIFO 5MBPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16DP-26 | 制造商:Thomas & Betts 功能描述:SAXXIT CABLE CLIP W/ DRIVE PIN -7 制造商:Belden Inc 功能描述: |
| SC16DP-3Q | 制造商:Thomas & Betts 功能描述:SAXXIT CABLE CLIP W/ DRIVE PIN -8 |
| SC16-FM-M16-NPB-ML-1 | 制造商:HellermannTyton 功能描述: |
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