參數(shù)資料
型號： SC16C852VIET,157
廠商： NXP Semiconductors
文件頁數(shù)： 20/55頁
文件大?。?/td> 0K
描述： IC UART DUAL W/FIFO 36TFBGA
產(chǎn)品培訓模塊： Stand-Alone UARTs
標準包裝： 2,450
特點： 可編程
通道數(shù)： 2，DUART
FIFO's： 128 字節(jié)
規(guī)程： RS485
電源電壓： 2.5V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 36-TFBGA
供應商設備封裝： 36-TFBGA（3.5x3.5）
包裝： 托盤
其它名稱： 568-4019
935282518157
SC16C852VIET
SC16C852VIET-ND
SC16C852V
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 21 January 2011
27 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.4 Interrupt Status Register (ISR)
The SC16C852V provides six levels of prioritized interrupts to minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. A lower level interrupt may be seen after servicing the higher level
interrupt and re-reading the interrupt status bits. Table 14 “Interrupt source” shows the
data values (bits 5:0) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
Table 14.
Interrupt source
Priority
level
ISR[5] ISR[4] ISR[3] ISR[2] ISR[1] ISR[0] Source of the interrupt
1
000110
LSR (Receiver Line Status Register)
2
000100
RXRDY (Received Data Ready)
2
001100
RXRDY (Receive Data time-out)
3
000010
TXRDY (Transmitter Holding
Register Empty)
4
000000
MSR (Modem Status Register)
5
010000
RXRDY (Received Xoff signal)/
Special character
6
100000
CTS, RTS change of state
Table 15.
Interrupt Status Register bits description
Bit
Symbol
Description
7:6
ISR[7:6]
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being
used in the non-FIFO mode. They are set to a logic 1 when the FIFOs are
enabled in the SC16C852V mode.
logic 0 or cleared = default condition
5:4
ISR[5:4]
INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.
ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]
indicates that CTS, RTS have been generated. Note that once set to a
logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.
logic 0 or cleared = default condition
3:1
ISR[3:1]
INT priority bits 2:0. These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2, and 3 (see Table 14).
logic 0 or cleared = default condition
0
ISR[0]
INT status.
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
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