參數(shù)資料
型號(hào): SC16C852VIET,115
廠商: NXP Semiconductors
文件頁數(shù): 29/55頁
文件大小: 0K
描述: IC UART DUAL W/FIFO 36TFBGA
標(biāo)準(zhǔn)包裝: 1,000
特點(diǎn): 可編程
通道數(shù): 2,DUART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.5V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 36-TFBGA
供應(yīng)商設(shè)備封裝: 36-TFBGA(3.5x3.5)
包裝: 帶卷 (TR)
其它名稱: 935282518115
SC16C852VIET-G
SC16C852VIET-G-ND
SC16C852V
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 21 January 2011
35 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.17 Flow Control Trigger Level High (FLWCNTH)
This 8-bit register is used to store the receive FIFO high threshold levels to start/stop
transmission during hardware/software flow control. Table 29 shows transmission control
register bit settings; see Section 6.5.
[1]
For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.
7.18 Flow Control Trigger Level Low (FLWCNTL)
This 8-bit register is used to store the receive FIFO low threshold levels to start/stop
transmission during hardware/software flow control. Table 30 shows transmission control
register bit settings; see Section 6.5.
[1]
For 32-byte FIFO mode, refer to Section 7.3 “FIFO Control Register (FCR)”.
7.19 Clock prescaler (CLKPRES)
This register hold values for the clock prescaler.
Table 29.
FLWCNTH register bits description
Bit
Symbol
Description
7:0
FLWCNTH[7:0]
This register stores the programmable HIGH threshold level for
hardware and software flow control for 128-byte FIFO mode.[1]
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Table 30.
FLWCNTL register bits description
Bit
Symbol
Description
7:0
FLWCNTL[7:0]
This register stores the programmable LOW threshold level for
hardware and software flow control for 128-byte FIFO mode.[1]
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Table 31.
Clock prescaler register description
Bit
Symbol
Description
7:4
CLKPRES[7:4]
reserved
3:0
CLKPRES[3:0]
clock prescaler value; reset to 0
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