參數(shù)資料
型號： SC16C852VIET,115
廠商： NXP Semiconductors
文件頁數(shù)： 22/55頁
文件大?。?/td> 0K
描述： IC UART DUAL W/FIFO 36TFBGA
標準包裝： 1,000
特點： 可編程
通道數(shù)： 2，DUART
FIFO's： 128 字節(jié)
規(guī)程： RS485
電源電壓： 2.5V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 36-TFBGA
供應(yīng)商設(shè)備封裝： 36-TFBGA（3.5x3.5）
包裝： 帶卷 (TR)
其它名稱： 935282518115
SC16C852VIET-G
SC16C852VIET-G-ND
SC16C852V
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 21 January 2011
29 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 20.
Modem Control Register bits description
Bit
Symbol Description
7
MCR[7]
Clock select
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
6
MCR[6]
IR enable (see Figure 21).
logic 0 = enable the standard modem receive and transmit input/output interface
(normal default condition)
logic 1 = enable infrared IrDA receive and transmit inputs/outputs. While in this
mode, the TX/RX output/inputs are routed to the infrared encoder/decoder. The
data input and output levels will conform to the IrDA infrared interface
requirement. As such, while in this mode, the infrared TX output will be a logic 0
during idle data conditions.
5
MCR[5]
Reserved; set to ‘0’.
4
MCR[4]
Loopback. Enable the local Loopback mode (diagnostics). In this mode the
transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI are
disconnected from the SC16C852V I/O pins. Internally the modem data and
control pins are connected into a loopback data configuration (see Figure 9). In
this mode, the receiver and transmitter interrupts remain fully operational. The
Modem Control Interrupts are also operational, but the interrupts’ sources are
switched to the lower four bits of the Modem Control. Interrupts continue to be
controlled by the IER register.
logic 0 = disable Loopback mode (normal default condition)
logic 1 = enable local Loopback mode (diagnostics)
3
MCR[3]
OP2A/OP2B, INT enable
logic 0 = forces INT (A, B) outputs to the 3-state mode and sets OP2A/OP2B to
a logic 1 (normal default condition)
logic 1 = forces the INT (A, B) outputs to the active mode and sets OP2A/OP2B
to a logic 0
Remark: OP2A/OP2B pins do not exist on the TFBGA36 package.
2
MCR[2]
OP1A/OP1B are not available as an external signal in the SC16C852V. This bit is
instead used in the Loopback mode only. In the Loopback mode, this bit is used to
write the state of the modem RI interface signal.
1
MCR[1]
RTS
logic 0 = force RTS output to a logic 1 (normal default condition)
logic 1 = force RTS output to a logic 0
0
MCR[0]
DTR
logic 0 = force DTR output to a logic 1 (normal default condition)
logic 1 = force DTR output to a logic 0
Table 21.
Interrupt output control
MCR[3]
INT (A, B) output
03-state
1active
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