參數(shù)資料
型號: SC16C852SVIET
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 1.8 V dual UART, 20 Mbit-s (max.) with 128-byte FIFOs, infrared (IrDA), and XScale VLIO bus interface
中文描述: 2 CHANNEL(S), 5M bps, SERIAL COMM CONTROLLER, PBGA36
封裝: 3.50 X 3.50 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, PLASTIC, SOT-912-1, TFBGA-36
文件頁數(shù): 26/48頁
文件大?。?/td> 221K
代理商: SC16C852SVIET
SC16C852SV_1
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 23 September 2008
26 of 48
NXP Semiconductors
SC16C852SV
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 14.
Bit
7
Line Control Register bits description
Symbol
Description
LCR[7]
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
LCR[6]
Set break. When enabled, the Break control bit causes a break condition to
be transmitted (the TX output is forced to a logic 0 state). This condition
exists until disabled by setting LCR[6] to a logic 0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
LCR[5:3]
Programs the parity conditions (see
Table 15
).
LCR[2]
Stop bits. The length of stop bit is specified by this bit in conjunction with the
programmed word length (see
Table 16
).
logic 0 or cleared = default condition
LCR[1:0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
Table 17
).
logic 0 or cleared = default condition
6
5:3
2
1:0
Table 15.
LCR[5]
X
X
0
0
1
LCR[5:3] parity selection
LCR[4]
LCR[3]
X
0
0
1
1
1
0
1
1
1
Parity selection
no parity
odd parity
even parity
forced parity ‘1’
forced parity ‘0’
Table 16.
LCR[2]
0
1
1
LCR[2] stop bit length
Word length (bits)
5, 6, 7, 8
5
6, 7, 8
Stop bit length (bit times)
1
1
1
2
2
Table 17.
LCR[1]
0
0
1
1
LCR[1:0] word length
LCR[0]
0
1
0
1
Word length (bits)
5
6
7
8
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