參數(shù)資料
型號: SC16C754BIA68
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.) with 64-byte FIFOs
封裝: SC16C754BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html<1<Always Pb-free,;SC16C754BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html&
文件頁數(shù): 29/51頁
文件大小: 253K
代理商: SC16C754BIA68
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
29 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.8 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from LOW
to HIGH. The INT output signal is activated in response to interrupt generation.
Table 16
shows the interrupt enable register bit settings.
[1]
IER[7:4] can only be modified if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will
cause a new interrupt if the THR is below the threshold.
Table 16.
Bit
7
Interrupt enable register bits description
Symbol
Description
IER[7]
[1]
CTS interrupt enable.
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt
IER[6]
[1]
RTS interrupt enable.
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt
IER[5]
[1]
Xoff interrupt.
logic 0 = disable the Xoff interrupt (normal default condition)
logic 1 = enable the Xoff interrupt
IER[4]
[1]
Sleep mode.
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See
Section 6.7 “Sleep mode”
for details.
IER[3]
Modem status interrupt.
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt
IER[2]
Receive line status interrupt.
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
IER[1]
Transmit holding register interrupt.
logic 0 = disable the THR interrupt (normal default condition)
logic 1 = enable the THR interrupt
IER[0]
Receive holding register interrupt.
logic 0 = disable the RHR interrupt (normal default condition)
logic 1 = enable the RHR interrupt
6
5
4
3
2
1
0
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