參數(shù)資料
型號: SC16C754BIA68
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.) with 64-byte FIFOs
封裝: SC16C754BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html<1<Always Pb-free,;SC16C754BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html&
文件頁數(shù): 28/51頁
文件大?。?/td> 253K
代理商: SC16C754BIA68
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
28 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.7 Modem Status Register (MSR)
This 8-bit register provides information about the current state of the control lines from the
modem, data set, or peripheral device to the processor. It also indicates when a control
input from the modem changes state.
Table 15
shows modem status register bit settings
per channel.
[1]
The primary inputs RI, CD, CTS, DSR are all active LOW, but their registered equivalents in the MSR and
MCR (in loopback) registers are active HIGH.
Table 15.
Bit
7
Modem status register bits description
Symbol
Description
MSR[7]
[1]
CD (active HIGH, logic 1). This bit is the complement of the CD input during
normal mode. During internal loopback mode, it is equivalent to MCR[3].
MSR[6]
[1]
RI (active HIGH, logic 1). This bit is the complement of the RI input during
normal mode. During internal loopback mode, it is equivalent to MCR[2].
MSR[5]
[1]
DSR (active HIGH, logic 1). This bit is the complement of the DSR input
during normal mode. During internal loopback mode, it is equivalent MCR[0].
MSR[4]
[1]
CTS (active HIGH, logic 1). This bit is the complement of the CTS input
during normal mode. During internal loopback mode, it is equivalent to
MCR[1].
MSR[3]
CD. Indicates that CD input (or MCR[3] in loopback mode) has changed
state. Cleared on a read.
MSR[2]
RI. Indicates that RI input (or MCR[2] in loopback mode) has changed state
from LOW to HIGH. Cleared on a read.
MSR[1]
DSR. Indicates that DSR input (or MCR[0] in loopback mode) has changed
state. Cleared on a read.
MSR[0]
CTS. Indicates that CTS input (or MCR[1] in loopback mode) has changed
state. Cleared on a read.
6
5
4
3
2
1
0
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