參數(shù)資料
型號: SC16C654BIBM
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.), with 64-byte FIFOs and infrared (IrDA) encoder-decoder
封裝: SC16C654BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html<1<Always Pb-free,;SC16C654BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html&
文件頁數(shù): 25/58頁
文件大?。?/td> 302K
代理商: SC16C654BIBM
9397 750 14965
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 20 June 2005
25 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.1 Transmit (THR) and Receive (RHR) Holding Registers
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the
THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will
be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.
Note that a write operation can be performed when the THR empty flag is set
(logic 0 = FIFO full; logic 1 = at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C654B/654DB and receive FIFO by reading the
RHR register. The receive section provides a mechanism to prevent false starts. On the
falling edge of a start or false start bit, an internal receiver counter starts counting clocks
at the 16
×
clock rate. After 7
1
2
clocks, the start bit time should be shifted to the center of
the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTA to INTD output pins in the 16 mode, or on wire-OR IRQ output pin in the
68 mode.
Table 9:
Bit
7
Interrupt Enable Register bits description
Symbol
Description
IER[7]
CTS interrupt.
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt. The SC16C654B/654DB issues an
interrupt when the CTS pin transitions from a logic 0 to a logic 1.
IER[6]
RTS interrupt.
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt. The SC16C654B/654DB issues an
interrupt when the RTS pin transitions from a logic 0 to a logic 1.
IER[5]
Xoff interrupt.
logic 0 = disable the software flow control, receive Xoff interrupt (normal
default condition)
logic 1 = enable the software flow control, receive Xoff interrupt. See
Section
6.5 “Software flow control”
for details.
IER[4]
Sleep mode.
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See
Section 6.11 “Sleep mode”
for details.
IER[3]
Modem Status Interrupt.
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt
6
5
4
3
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