參數(shù)資料
型號: SC16C654BIA68
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.), with 64-byte FIFOs and infrared (IrDA) encoder-decoder
封裝: SC16C654BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html<1<Always Pb-free,;SC16C654BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html&
文件頁數(shù): 36/58頁
文件大小: 302K
代理商: SC16C654BIA68
9397 750 14965
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 20 June 2005
36 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
[1]
When using software flow control the Xon/Xoff characters cannot be used for data transfer.
7.11 SC16C654B/654DB external reset conditions
Table 23:
Cont-3
0
1
0
1
X
X
X
1
Software flow control functions
[1]
Cont-2
Cont-1
0
X
0
X
1
X
1
X
X
0
X
1
X
0
0
1
Cont-0
X
X
X
X
0
0
1
1
TX, RX software flow controls
no transmit flow control
transmit Xon1/Xoff1
transmit Xon2/Xoff2
transmit Xon1 and Xon2/Xoff1 and Xoff2
no receive flow control
receiver compares Xon1/Xoff1
receiver compares Xon2/Xoff2
transmit Xon1/Xoff1
receiver compares Xon1 and Xon2, Xoff1 and Xoff2
transmit Xon2/Xoff2
receiver compares Xon1 and Xon2/Xoff1 and Xoff2
transmit Xon1 and Xon2/Xoff1 and Xoff2
receiver compares Xon1 and Xon2/Xoff1 and Xoff2
0
1
1
1
1
1
1
1
Table 24:
Register
IER
ISR
LCR
MCR
LSR
MSR
FCR
EFR
Reset state for registers
Reset state
IER[7:0] = 0
ISR[7:1] = 0; ISR[0] = 1
LCR[7:0] = 0
MCR[7:0] = 0
LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0
MSR[7:4] = input signals; MSR[3:0] = 0
FCR[7:0] = 0
EFR[7:0] = 0
Table 25:
Output
TXA, TXB, TXC, TXD
RTSA, RTSB, RTSC, RTSD
DTRA, DTRB, DTRC, DTRD
RXRDY
TXRDY
Reset state for outputs
Reset state
HIGH
HIGH
HIGH
HIGH
LOW
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SC16C654B 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoder
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