參數(shù)資料
型號: SC16C654BIA68
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.), with 64-byte FIFOs and infrared (IrDA) encoder-decoder
封裝: SC16C654BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html<1<Always Pb-free,;SC16C654BIA68<SOT188-2 (PLCC68)|<<http://www.nxp.com/packages/SOT188-2.html&
文件頁數(shù): 32/58頁
文件大?。?/td> 302K
代理商: SC16C654BIA68
9397 750 14965
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 20 June 2005
32 of 58
Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
4
MCR[4]
Loop-back. Enable the local loop-back mode (diagnostics). In this mode the
transmitter output (TX) and the receiver input (RX), CTS, DSR, CD, and RI are
disconnected from the SC16C654B/654DB I/O pins. Internally the modem
data and control pins are connected into a loop-back data configuration; see
Figure 12
. In this mode, the receiver and transmitter interrupts remain fully
operational. The Modem Control Interrupts are also operational, but the
interrupts’ sources are switched to the lower four bits of the Modem Control.
Interrupts continue to be controlled by the IER register.
logic 0 = disable loop-back mode (normal default condition)
logic 1 = enable local loop-back mode (diagnostics)
OP2, INTx enable. Used to control the modem CD signal in the loop-back
mode.
logic 0 = forces INTA-INTD outputs to the 3-state mode during the 16 mode
(normal default condition). In the loop-back mode, sets OP2 (CD) internally
to a logic 1.
logic 1 = forces the INTA-INTD outputs to the active mode during the
16 mode. In the loop-back mode, sets OP2 (CD) internally to a logic 0.
OP1. This bit is used in the Loop-back mode only. In the loop-back mode, this
bit is used to write the state of the modem RI interface signal via OP1.
RTS
logic 0 = force RTS output to a logic 1 (normal default condition)
logic 1 = force RTS output to a logic 0
Automatic RTS may be used for hardware flow control by enabling EFR[6].
See
Table 22
.
DTR
logic 0 = force DTR output to a logic 1 (normal default condition)
logic 1 = force DTR output to a logic 0
3
MCR[3]
2
MCR[2]
1
MCR[1]
0
MCR[0]
Table 19:
Bit
Modem Control Register bits description
…continued
Symbol
Description
相關(guān)PDF資料
PDF描述
SC16C654B 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byte FIFOs and infrared (IrDA) encoder/decoder
SC16C654BIB64 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.), with 64-byte FIFOs and infrared (IrDA) encoder-decoder
SC16C654BIBM 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.), with 64-byte FIFOs and infrared (IrDA) encoder-decoder
SC16C654BIBS 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.), with 64-byte FIFOs and infrared (IrDA) encoder-decoder
SC16C654DBIB64 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit-s (max.), with 64-byte FIFOs and infrared (IrDA) encoder-decoder
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