參數(shù)資料
型號(hào): SC16C652B
廠商: NXP Semiconductors N.V.
英文描述: 5V, 3.3 V and 2.5V dual UART, 5 Mbit/s (max.),with 32-byte FIFOs and infrared(IrDA) encoder/decoder
中文描述: 5V的,3.3V和2.5V雙,5兆的UART /秒(最大),32字節(jié)的FIFO和紅外線(IrDA)編碼器/解碼器
文件頁(yè)數(shù): 30/44頁(yè)
文件大?。?/td> 205K
代理商: SC16C652B
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Product data
Rev. 03 — 10 December 2004
30 of 44
9397 750 14452
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
10. Dynamic characteristics
[1]
Applies to external clock, crystal oscillator max 24 MHz.
Table 29:
T
amb
=
40
°
C to +85
°
C; V
CC
= 2.5 V 3.3 V or 5.0 V
±
10%, unless otherwise specified.
Symbol
Parameter
AC electrical characteristics
Conditions
2.5 V
3.3 V
Max
-
80
-
-
-
-
-
-
26
15
-
-
-
-
-
-
33
24
24
1
29
45
24
45
1
45
45
8
-
2
16
1 1
5.0 V
Max
-
80
-
-
-
-
-
-
23
15
-
-
-
-
-
-
29
23
23
1
28
40
24
40
1
40
40
8
-
2
16
1 R
clk
Unit
Min
10
-
0
0
10
77
0
20
-
-
10
20
0
25
20
15
-
-
-
-
-
-
8
-
-
-
-
-
200
1
Max
-
48
-
-
-
-
-
-
77
15
-
-
-
-
-
-
100
100
100
1
100
100
24
100
1
100
100
8
-
2
16
1 1
Min
6
-
0
0
10
26
0
20
-
-
10
20
0
25
20
5
-
-
-
-
-
-
8
-
-
-
-
-
40
Min
6
t
1w
, t
2w
t
3w
t
6s
t
6h
t
7d
t
7w
t
7h
t
9d
t
12d
t
12h
t
13d
t
13w
t
13h
t
15d
t
16s
t
16h
t
17d
t
18d
t
19d
t
20d
t
21d
t
22d
t
23d
t
24d
t
25d
t
26d
t
27d
t
28d
t
RESET
N
clock pulse duration
oscillator/clock frequency
address set-up time
address hold time
IOR delay from chip select
IOR strobe width
chip select hold time from IOR
read cycle delay
delay from IOR to data
data disable time
IOW delay from chip select
IOW strobe width
chip select hold time from IOW
write cycle delay
data set-up time
data hold time
delay from IOW to output
delay to set interrupt from Modem input 25 pF load
delay to reset interrupt from IOR
delay from stop to set interrupt
delay from IOR to reset interrupt
delay from start to set interrupt
delay from IOW to transmit start
delay from IOW to reset interrupt
delay from stop to set RXRDY
delay from IOR to reset RXRDY
delay from IOW to set TXRDY
delay from start to reset TXRDY
Reset pulse width
baud rate divisor
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
clk
ns
ns
R
clk
ns
R
clk
ns
ns
R
clk
ns
[1]
0
0
10
23
0
20
-
-
10
15
0
20
15
5
-
-
-
-
-
-
8
-
-
-
-
-
40
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
25 pF load
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