參數(shù)資料
型號(hào): SC16C652B
廠商: NXP Semiconductors N.V.
英文描述: 5V, 3.3 V and 2.5V dual UART, 5 Mbit/s (max.),with 32-byte FIFOs and infrared(IrDA) encoder/decoder
中文描述: 5V的,3.3V和2.5V雙,5兆的UART /秒(最大),32字節(jié)的FIFO和紅外線(IrDA)編碼器/解碼器
文件頁(yè)數(shù): 27/44頁(yè)
文件大小: 205K
代理商: SC16C652B
Philips Semiconductors
SC16C652B
Dual UART with 32-byte FIFOs and IrDA encoder/decoder
Product data
Rev. 03 — 10 December 2004
27 of 44
9397 750 14452
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
When using a software flow control the Xon/Xoff characters cannot be used for data transfer.
5
EFR[5]
Special Character Detect.
Logic 0 = Special character detect disabled (normal default condition).
Logic 1 = Special character detect enabled. The SC16C652B compares
each incoming receive character with Xoff2 data. If a match exists, the
received data will be transferred to FIFO and ISR[4] will be set to
indicate detection of special character. Bit-0 in the X-registers
corresponds with the LSB bit for the receive character. When this feature
is enabled, the normal software flow control must be disabled (EFR[3:0]
must be set to a logic 0).
Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4],
and MCR[7:5] can be modified and latched. After modifying any bits in the
enhanced registers, EFR[4] can be set to a logic 0 to latch the new values.
This feature prevents existing software from altering or overwriting the
SC16C652B enhanced functions.
Logic 0 = disable/latch enhanced features. IER[7:4], ISR[5:4], FCR[5:4],
and MCR[7:5] are saved to retain the user settings, then IER[7:4]
ISR[5:4], FCR[5:4], and MCR[7:5] are set to a logic 0 to be compatible
with SC16C554 mode. (Normal default condition.)
Logic 1 = Enables the enhanced functions. When this bit is set to a
logic 1, all enhanced features of the SC16C652B are enabled and user
settings stored during a reset will be restored.
Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition.
Combinations of software flow control can be selected by programming
these bits. See
Table 24
.
4
EFR[4]
3:0
EFR[3:0]
Table 24:
Cont-3
0
1
0
1
X
X
X
1
Software flow control functions
[1]
Cont-2
Cont-1
0
X
0
X
1
X
1
X
X
0
X
1
X
0
0
1
Cont-0
X
X
X
X
0
0
1
1
TX, RX software flow controls
No transmit flow control
Transmit Xon1/Xoff1
Transmit Xon2/Xoff2
Transmit Xon1 and Xon2/Xoff1 and Xoff2
No receive flow control
Receiver compares Xon1/Xoff1
Receiver compares Xon2/Xoff2
Transmit Xon1/Xoff1
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
Transmit Xon2/Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
Transmit Xon1 and Xon2/Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
0
1
1
1
1
1
1
1
Table 23:
Bit
Enhanced Feature Register bits description
…continued
Symbol
Description
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