參數(shù)資料
型號(hào): SC16C550BIN40
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
中文描述: 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PDIP40
封裝: 0.600 INCH, PLASTIC, MO-015, SOT-129-1, DIP-40
文件頁數(shù): 26/47頁
文件大?。?/td> 229K
代理商: SC16C550BIN40
Philips Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Product data
Rev. 02 — 14 December 2004
26 of 47
9397 750 14446
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 19:
Bit
7
6
5
4
Modem Control Register bits description
Symbol
Description
MCR[7]
Reserved; set to ‘0’.
MCR[6]
Reserved; set to ‘0’.
MCR[5]
Auto flow control enable.
MCR[4]
Loop-back. Enable the local loop-back mode (diagnostics). In this
mode the transmitter output (TX) and the receiver input (RX), CTS,
DSR, DCD, and RI are disconnected from the SC16C550B I/O pins.
Internally the modem data and control pins are connected into a
loop-back data configuration (see
Figure 10
). In this mode, the
receiver and transmitter interrupts remain fully operational. The
Modem Control Interrupts are also operational, but the interrupts’
sources are switched to the lower four bits of the Modem Control.
Interrupts continue to be controlled by the IER register.
Logic 0 = Disable loop-back mode (normal default condition).
Logic 1 = Enable local loop-back mode (diagnostics).
MCR[3]
OUT2, INTx enable. Used to control the modem DCD signal in the
loop-back mode.
Logic 0 = Forces INT output to the 3-State mode. In the loop-back
mode, sets OUT2 (DCD) internally to a logic 1.
Logic 1 = Forces the INT output to the active mode. In the
loop-back mode, sets OUT2 (DCD) internally to a logic 0.
MCR[2]
OUT1. This bit is used in the Loop-back mode only. In the loop-back
mode, this bit is used to write the state of the modem RI interface
signal via OUT1.
MCR[1]
RTS
Logic 0 = Force RTS output to a logic 1 (normal default condition).
Logic 1 = Force RTS output to a logic 0.
MCR[0]
DTR
Logic 0 = Force DTR output to a logic 1 (normal default condition).
Logic 1 = Force DTR output to a logic 0.
3
2
1
0
相關(guān)PDF資料
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SC16C550IN40 Universal Asynchronous Receiver/Transmitter (UART) with 16-byte FIFO and infrared (IrDA) encoder/decoder
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