參數(shù)資料
型號: SC16C550BIB48
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
封裝: SC16C550BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html<1<week 51, 2004,;SC16C550BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html&l
文件頁數(shù): 31/48頁
文件大小: 240K
代理商: SC16C550BIB48
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Dynamic characteristics
…continued
T
amb
=
40
°
C to +85
°
C; tolerance of V
DD
±
10 %, unless otherwise specified.
Symbol
Parameter
Conditions
V
DD
= 2.5 V
Min
S
P
R
3
N
S
5
[1]
Applies to external clock, crystal oscillator max 24 MHz.
[2]
Maximum frequency =
[3]
Applicable only when AS is tied LOW.
[4]
RESET pulse must happen when these signals are inactive: CS0 or CS1 or CS2 or CS, and IOW, IOR.
t
20d
t
21d
t
22d
t
23d
t
24d
t
25d
t
26d
t
27d
t
28d
t
RESET
N
delay from stop to set interrupt
delay from IOR to reset interrupt
delay from start to set interrupt
delay from IOW to transmit start
delay from IOW to reset interrupt
delay from stop to set RXRDY
delay from IOR to reset RXRDY
delay from IOW to set TXRDY
delay from start to reset TXRDY
RESET pulse width
baud rate divisor
-
-
-
8T
RCLK
-
-
-
-
-
1T
RCLK
100
100
24T
RCLK
100
1T
RCLK
100
100
8T
RCLK
-
2
16
1
-
-
-
8T
RCLK
-
-
-
-
-
40
1
1T
RCLK
29
45
24T
RCLK
45
1T
RCLK
45
45
8T
RCLK
-
2
16
1
-
-
-
8T
RCLK
-
-
-
-
-
40
1
1T
RCLK
28
40
24T
RCLK
40
1T
RCLK
40
40
8T
RCLK
-
2
16
1
s
ns
ns
s
ns
s
ns
ns
s
ns
25 pF load
[4]
100
1
Table 26.
V
DD
= 3.3 V
Min
V
DD
= 5.0 V
Min
Unit
Max
Max
Max
w3
-------
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