參數(shù)資料
型號(hào): SC16C2550BIB48
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit-s (max.), with 16-byte FIFOs
封裝: SC16C2550BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html<1<week 51, 2004,;SC16C2550BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html
文件頁數(shù): 23/43頁
文件大?。?/td> 211K
代理商: SC16C2550BIB48
SC16C2550B_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 January 2009
23 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the modem or
other peripheral device to which the SC16C2550B is connected. Four bits of this register
are used to indicate the changed information. These bits are set to a logic 1 whenever a
control input from the modem changes state. These bits are set to a logic 0 whenever the
CPU reads this register.
[1]
Whenever any MSR bit 3:0 is set to logic 1, a Modem Status Interrupt will be generated.
0
LSR[0]
Receive data ready.
logic 0 = no data in Receive Holding Register or FIFO (normal default
condition)
logic 1 = data has been received and is saved in the Receive Holding Register
or FIFO
Table 19.
Bit
Line Status Register bits description
…continued
Symbol
Description
Table 20.
Bit
7
Modem Status Register bits description
Symbol
Description
MSR[7]
CD. During normal operation, this bit is the complement of the CD input.
Reading this bit in the Loopback mode produces the state of MCR[3] (OP2).
MSR[6]
RI. During normal operation, this bit is the complement of the RI input.
Reading this bit in the Loopback mode produces the state of MCR[2] (OP1).
MSR[5]
DSR. During normal operation, this bit is the complement of the DSR input.
During the Loopback mode, this bit is equivalent to MCR[0] (DTR).
MSR[4]
CTS. During normal operation, this bit is the complement of the CTS input.
During the Loopback mode, this bit is equivalent to MCR[1] (RTS).
MSR[3]
CD
[1]
logic 0 = no CD change (normal default condition)
logic 1 = the CD input to the SC16C2550B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
MSR[2]
RI
[1]
logic 0 = no RI change (normal default condition)
logic 1 = the RI input to the SC16C2550B has changed from a logic 0 to a
logic 1. A modem Status Interrupt will be generated.
MSR[1]
DSR
[1]
logic 0 = no DSR change (normal default condition)
logic 1 = the DSR input to the SC16C2550B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
MSR[0]
CTS
[1]
logic 0 = no CTS change (normal default condition)
logic 1 = the CTS input to the SC16C2550B has changed state since the
last time it was read. A modem Status Interrupt will be generated.
6
5
4
3
2
1
0
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