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| 型號(hào)： | SC16C2550BIB48 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 收發(fā)器 |
| 英文描述： | 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit-s (max.), with 16-byte FIFOs |
| 封裝： | SC16C2550BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html<1<week 51, 2004,;SC16C2550BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html |
| 文件頁數(shù)： | 20/43頁 |
| 文件大?。?/td> | 211K |
| 代理商： | SC16C2550BIB48 |
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SC16C2550B_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 January 2009
20 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits and the parity are selected by writing the
appropriate bits in this register.
Table 13.
Bit
7:6
Interrupt Status Register bits description
Symbol
Description
ISR[7:6]
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not
being used in the 16C450 mode. They are set to a logic 1 when the
FIFOs are enabled in the SC16C2550B mode.
logic 0 or cleared = default condition
ISR[5:4]
not used
ISR[3:1]
INT priority bits 2:0. These bits indicate the source for a pending interrupt
at interrupt priority levels 1, 2 and 3 (see
Table 12
).
logic 0 or cleared = default condition
ISR[0]
INT status.
logic 0 = an interrupt is pending and the ISR contents may be used as
a pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
5:4
3:1
0
Table 14.
Bit
7
Line Control Register bits description
Symbol
Description
LCR[7]
Divisor latch enable. The internal baud rate counter latch and Enhanced
Feature mode enable.
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch enabled
LCR[6]
Set break. When enabled, the Break control bit causes a break condition
to be transmitted (the TX output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic 0.
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
LCR[5:3]
Programs the parity conditions (see
Table 15
)
LCR[2]
Stop bits. The length of stop bit is specified by this bit in conjunction with
the programmed word length (see
Table 16
).
logic 0 or cleared = default condition
LCR[1:0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
Table 17
).
logic 0 or cleared = default condition
6
5:3
2
1:0
Table 15.
LCR[5]
X
X
0
0
1
LCR[5:3] parity selection
LCR[4]
X
0
1
0
1
LCR[3]
0
1
1
1
1
Parity selection
no parity
odd parity
even parity
forced parity ‘1’
forced parity ‘0’
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PDF描述 |
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| SC16C2550BIBS | 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit-s (max.), with 16-byte FIFOs |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C2550BIB48,128 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C2550BIB48,151 | 功能描述:UART 接口集成電路 2CH. UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C2550BIB48,157 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C2550BIB48-S | 功能描述:UART 接口集成電路 2CH. UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C2550BIBS | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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