參數(shù)資料
型號: SC16C2550BIA44
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit-s (max.), with 16-byte FIFOs
封裝: SC16C2550BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html<1<week 51, 2004,;SC16C2550BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html
文件頁數(shù): 41/43頁
文件大?。?/td> 211K
代理商: SC16C2550BIA44
SC16C2550B_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 January 2009
41 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
15. Revision history
Table 30.
Document ID
SC16C2550B_5
Modifications:
Revision history
Release date
20090112
Section 2 “Features”
: 3
rd
bullet item changed from “5 V tolerant inputs” to “5 V tolerant on input
only pins” and added
Footnote 1
.
Figure 7 “Internal Loopback mode diagram”
:
at signals coming out of ‘modem control logic’ block, changed from “OP1A, OP2B” to
“OP1A, OP1B”
Table 23 “Limiting values”
:
symbol V
n
split to show 2 separate conditions: “at D7 to D0 pins” and “at input only pins”
Table 24 “Static characteristics”
:
changed symbol/parameter from “V
IL(CK)
, LOW-level clock input voltage” to “V
IL(clk)
, clock
LOW-level input voltage”
changed symbol/parameter from “V
IH(CK)
, HIGH-level clock input voltage” to “V
IH(clk)
, clock
HIGH-level input voltage”
changed symbol/parameter from “I
CL
, clock leakage” to “I
L(clk)
, clock leakage current”
Table 25 “Dynamic characteristics”
: added
Table note [4]
and its reference at t
RESET
updated soldering information
20070215
Product data sheet
20050926
Product data sheet
20041214
Product data
Data sheet status
Product data sheet
Change notice
-
Supersedes
SC16C2550B_4
SC16C2550B_4
SC16C2550B_3
SC16C2550B-02
(9397 750 14449)
SC16C2550B-01
(9397 750 11982)
-
-
-
SC16C2550B_3
SC16C2550B-02
SC16C2550B-01
20050719
Product data
-
-
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