參數資料
型號: SC16C2550BIA44
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit-s (max.), with 16-byte FIFOs
封裝: SC16C2550BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html<1<week 51, 2004,;SC16C2550BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html
文件頁數: 14/43頁
文件大?。?/td> 211K
代理商: SC16C2550BIA44
SC16C2550B_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 January 2009
14 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
converts the serial data back into parallel data that is then made available at the user data
interface D0 through D7. The user optionally compares the received data to the initial
transmitted data for verifying error-free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The modem
control interrupts are also operational.
Fig 7.
Internal Loopback mode diagram
CTSA, CTSB
TRANSMIT
FIFO
REGISTERS
TXA, TXB
RECEIVE
SHIFT
REGISTER
RECEIVE
FIFO
REGISTERS
RXA, RXB
I
A
C
SC16C2550B
TRANSMIT
SHIFT
REGISTER
002aaa599
DATA BUS
AND
CONTROL
LOGIC
REGISTER
SELECT
LOGIC
INTERRUPT
CONTROL
LOGIC
D0 to D7
IOR
IOW
RESET
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
CLOCK AND
BAUD RATE
GENERATOR
MODEM
CONTROL
LOGIC
RTSA, RTSB
DSRA, DSRB
DTRA, DTRB
RIA, RIB
(OP1A, OP1B)
CDA, CDB
(OP2A, OP2B)
MCR[4] = 1
XTAL2
XTAL1
A0 to A2
CSA, CSB
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