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| 型號： | SC16C2550BIA44 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 收發(fā)器 |
| 英文描述： | 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit-s (max.), with 16-byte FIFOs |
| 封裝： | SC16C2550BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html<1<week 51, 2004,;SC16C2550BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html |
| 文件頁數(shù)： | 18/43頁 |
| 文件大?。?/td> | 211K |
| 代理商： | SC16C2550BIA44 |
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SC16C2550B_5
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 January 2009
18 of 43
NXP Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
regardless of the programmed level until the FIFO is full. RXRDY on PLCC44 and
LQFP48 packages transitions LOW when the FIFO reaches the trigger level and
transitions HIGH when the FIFO empties.
7.3.2
FIFO mode
Table 10.
Bit
7:6
FIFO Control Register bits description
Symbol
Description
FCR[7:6]
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
logic 0 (or cleared) = normal default condition
logic 1 = RX trigger level
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to be
loaded until it is full. Refer to
Table 11
.
FCR[5:4]
Not used; initialized to logic 0.
FCR[3]
DMA mode select.
logic 0 = set DMA mode ‘0’
logic 1 = set DMA mode ‘1’
Transmit operation in mode ‘0’:
When the SC16C2550B is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0) and when there are no
characters in the transmit FIFO or Transmit Holding Register, the TXRDYn
pin in PLCC44 or LQFP48 packages will be a logic 0. Once active, the
TXRDYn pin will go to a logic 1 after the first character is loaded into the
Transmit Holding Register.
Receive operation in mode ‘0’:
When the SC16C2550B is in mode ‘0’
(FCR[0] = logic 0) or in the FIFO mode (FCR[3] = logic 0) and there is at
least one character in the receive FIFO, the RXRDYn pin will be a logic 0.
Once active, the RXRDYn pin on PLCC44 and LQFP48 packages will go
to a logic 1 when there are no more characters in the receiver.
Transmit operation in mode ‘1’:
When the SC16C2550B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYn pin on PLCC44
and LQFP48 packages will be a logic 1 when the transmit FIFO is
completely full. It will be a logic 0 if one or more FIFO locations are empty.
Receive operation in mode ‘1’:
When the SC16C2550B is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been reached
or a Receive Time-out has occurred, the RXRDYn pin on PLCC44 and
LQFP48 packages will go to a logic 0. Once activated, it will go to a logic 1
after there are no more characters in the FIFO.
FCR[2]
XMIT FIFO reset.
logic 0 = Transmit FIFO not reset (normal default condition).
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the Transmit Shift Register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
5:4
3
2
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相關(guān)代理商/技術(shù)參數(shù) |
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| SC16C2550BIA44,512 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C2550BIA44,518 | 功能描述:UART 接口集成電路 2CH. UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C2550BIA44,518-CUT TAPE | 制造商:NXP 功能描述:SC16C2550B 5 V 3.3 V and 2.5 V Dual UART 5 Mbit/s w/ 16-byte FIFOs - PLCC44 |
| SC16C2550BIA44,529 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C2550BIA44512 | 制造商:NXP Semiconductors 功能描述:IC DUAL UART FIFO 5MBPS 5.5V LCC-44 |
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