參數(shù)資料
型號(hào)： SAK-XC2236N-24F80L
廠商： INFINEON TECHNOLOGIES AG
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP64
封裝： 0.50 MM PITCH, GREEN, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 96/110頁(yè)
文件大小： 1601K
代理商： SAK-XC2236N-24F80L
XC2232N, XC2234N, XC2236N, XC2238N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet
86
V1.3, 2010-04
Direct Drive
When direct drive operation is selected (SYSCON0.CLKSEL = 11
B), the system clock is
derived directly from the input clock signal CLKIN1:
f
SYS = fIN.
The frequency of
f
SYS is the same as the frequency of fIN. In this case the high and low
times of
f
SYS are determined by the duty cycle of the input clock fIN.
Selecting Bypass Operation from the XTAL1
1) input and using a divider factor of 1 results
in a similar configuration.
Prescaler Operation
When prescaler operation is selected (SYSCON0.CLKSEL = 10
B, PLLCON0.VCOBY =
1
B), the system clock is derived either from the crystal oscillator (input clock signal
XTAL1) or from the internal clock source through the output prescaler K1 (= K1DIV+1):
f
SYS = fOSC / K1.
If a divider factor of 1 is selected, the frequency of
f
SYS equals the frequency of fOSC. In
this case the high and low times of
f
SYS are determined by the duty cycle of the input
clock
f
OSC (external or internal).
The lowest system clock frequency results from selecting the maximum value for the
divider factor K1:
f
SYS = fOSC / 1024.
4.7.2.1
Phase Locked Loop (PLL)
When PLL operation is selected (SYSCON0.CLKSEL = 10
B, PLLCON0.VCOBY = 0B),
the on-chip phase locked loop is enabled and provides the system clock. The PLL
multiplies the input frequency by the factor F (
f
SYS = fIN × F).
F is calculated from the input divider P (= PDIV+1), the multiplication factor N (=
NDIV+1), and the output divider K2 (= K2DIV+1):
(F = N / (P
× K2)).
The input clock can be derived either from an external source at XTAL1 or from the on-
chip clock source.
The PLL circuit synchronizes the system clock to the input clock. This synchronization is
performed smoothly so that the system clock frequency does not change abruptly.
Adjustment to the input clock continuously changes the frequency of
f
SYS so that it is
locked to
f
IN. The slight variation causes a jitter of fSYS which in turn affects the duration
of individual TCSs.
1) Voltages on XTAL1 must comply to the core supply voltage
V
DDI1.
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