參數(shù)資料
型號(hào): SAF7118EH
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號(hào)轉(zhuǎn)換
英文描述: Multistandard video decoder with adaptive comb filter and component video input
中文描述: COLOR SIGNAL DECODER, PBGA156
封裝: 15 X 15 MM, 1.15 MM HEIGHT, PLASTIC, MS-034, SOT807-1, HBGA-156
文件頁數(shù): 146/173頁
文件大?。?/td> 950K
代理商: SAF7118EH
2004 Jul 22
146
Philips Semiconductors
Product speci
fi
cation
Multistandard video decoder with adaptive
comb
fi
lter and component video input
SAF7118
Table 104
I port I/O enable, output clock and gated clock phase control; global set 87H[7:4]; note 1
Notes
1.
2.
X = don’t care.
IPCK3 and IPCK2 only affects the gated clock (subaddress 80H, bit ICKS2 = 1).
Table 105
I port I/O enable, output clock and gated clock phase control; global set 87H[1:0]
OUTPUT CLOCK AND GATED CLOCK PHASE CONTROL
CONTROL BITS D7 TO D4
IPCK3
(2)
IPCK2
(2)
IPCK1
IPCK0
ICLK default output phase
ICLK phase shifted by
1
2
clock cycle
recommended for ICKS1 = 1
and ICKS0 = 0 (subaddress 80H)
ICLK phase shifted by approximately 3 ns
ICLK phase shifted by
1
2
clock cycle + approximately
3 ns
alternatively to setting ‘01’
IDQ = gated clock default output phase
IDQ = gated clock phase shifted by
1
2
clock cycle
recommended
for gated clock output
IDQ = gated clock phase shifted by approximately 3 ns
IDQ = gated clock phase shifted by
1
2
clock cycle + approximately
3 ns
alternatively to setting ‘01’
X
X
X
X
0
0
0
1
X
X
X
X
1
1
0
1
0
0
0
1
X
X
X
X
1
1
0
1
X
X
X
X
I PORT I/O ENABLE
CONTROL BITS D1 AND D0
IPE1
IPE0
I port output is disabled by software
I port output is enabled by software
I port output is enabled by pin ITRI at logic 0
I port output is enabled by pin ITRI at logic 1
0
0
1
1
0
1
0
1
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SAF7118H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multistandard video decoder with adaptive comb filter and component video input