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參數(shù)資料
| 型號： | SAA7893HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Super audio media player |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGTH, PLASTIC, SOT-425-1, LQFP-128 |
| 文件頁數(shù)： | 49/66頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | SAA7893HL |
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Philips Semiconductors
SAA7893HL
Super audio media player
Product data
Rev. 02 — 26 February 2003
49 of 66
9397 750 10925
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Both tables show that DSD has a fixed allocation while PCM outputs are selectable.
The I
2
S-bus bit stream, generated by the SAA7893HL decimation filter, is in the
Philips format as can be seen in the timing diagrams. The number of data bits is
always 24.
The wclk identification is always active for 32 clocks for each left and right sample,
except when the input clock is 384f
s
and the output sample frequency is 4f
s
; then the
wclk is 48 samples active.
11.2.1
DSD output
Remark:
in this example timing of the aud_clk is 256
×
f
s
and DSD clock phase is set
to logic 0. If phase is set to logic 1, the dsd_clk signal will be inverted.
Table 32:
Output line
Connection to a 4-channel DAC
Pin
number
DSD_PCM_8
117
DSD_PCM_9
120
DSD_PCM_10
119
DSD_PCM_11
121
Mode = DSD
Mode = PCM
Mode = 75 Hz
DSD clock
0 or 1
left channel
right channel
PCM data/word clock
PCM data/word clock
L
f
+ R
f
; 0 or 1
L
f
+ R
f
; 0 or 1
0 or 1
0 or 1
75 Hz
0 or 1
Table 33:
Audio input
clock
256f
s
Serial bit clock frequency
I
2
S output ‘wclk’
frequency
2f
s
4f
s
2f
s
4f
s
DCLK (data bit)
frequency
128f
s
256f
s
128f
s
384f
s
Remark
384f
s
no symmetrical bit clock
48 clocks for a word
identification
512f
s
2f
s
4f
s
2f
s
4f
s
128f
s
256f
s
128f
s
256f
s
768f
s
Fig 50. Audio I
2
S-bus output timing.
MBL629
dsd_clk (= 64fs)
aud_clk
dsd_pcm-data
SAMPLE N
SAMPLE N + 1
td(o)
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