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參數(shù)資料
| 型號： | SAA7893HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Super audio media player |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | 14 X 20 MM, 1.40 MM HEIGTH, PLASTIC, SOT-425-1, LQFP-128 |
| 文件頁數(shù)： | 19/66頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | SAA7893HL |
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Philips Semiconductors
SAA7893HL
Super audio media player
Product data
Rev. 02 — 26 February 2003
19 of 66
9397 750 10925
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
[1]
When the SAA7893HL SAD16 interface is programmed to generate always a H_WAIT signal of at least 7 sys_clk cycles, then it is no
longer required that the minimum time of t
tot
is 14 sys_clk cycles. The data at the H_DQ output is always available at the negative edge
of the H_WAIT signal. The host can deactivate the H_CS signal after the negative edge of the H_WAIT signal and when it has read the
data at the H_DQ lines. When a H_WAIT signal is always generated then the timing diagrams in
Figure 9
and
Figure 10
are no longer
applicable.
When the SAA7893HL SAD16 interface is programmed to generate always a H_WAIT signal, the minimum time will be 2 sys_clk cycles
and the maximum time will be 3 sys_clk cycles.
[2]
8.2.5
Host interface connection
8.3 SAD16_03 mode
To save physical pins on the SAA7893HL, the data bus is used to write the 16 MSB
address bits, hereafter called ‘the base address’, into the SAA7893HL. Therefore, to
access an address inside the SAA7893HL first this 16 MSB bits of the address must
be written as a base address for the SAA7893HL indicated by the H_A_sel line.
Pin H_A_sel can be mapped to a physical address pin of the host device.
t
wt(en)
t
tri
t
set
t
h(D)
time from H_WAIT negative slope to data set-up
time that data bus is set from 3-state to output
time that data is valid before CS is set to logic 1
hold time from CS to H_data bus
-
1
30
0
-
-
-
-
0
3
-
-
ns
sys_clk
ns
ns
Table 11:
Symbol
Timing numbers of reading registers via PI-bus
…continued
Parameter
Conditions
Min
Typ
Max
Unit
Fig 13. Host interface connection.
MCE039
H_RWn
CPU_RW
CE2n
CPU_WAIT
CPU_ADDR(7)
CPU_ADDR(6:1)
CPU_ADDR(15:0)
CPU_PROCCLK
IRQ_x
H_CSn
H_WAIT
27
24
26
H_A_sel
123
H_A[6:1]
124, 125, 126,
127, 128, 1
H_procclk
18
sys_clk
21
GND_IO
H_sel[0]
62
GND_IO
H_sel[1]
63
GND_IO
28
H_DQ[15:0]
H_IRQn
2, 3, 5, 6, 7, 8, 9,
11, 12, 13, 14,
15, 16, 22, 23, 25
10
k
SAA7893HL
SAD16_01
mode
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