參數(shù)資料
型號: SAA7710T
廠商: NXP Semiconductors N.V.
英文描述: High Quality Audio-Performance Digital Add-On Processor For Digital Sound Systems.(應用在數(shù)字聲音系統(tǒng)的高品質音頻性能數(shù)字附加處理器)
中文描述: 高品質音頻高性能數(shù)字加到了數(shù)字音響系統(tǒng)。(應用在數(shù)字聲音系統(tǒng)的高品質音頻性能數(shù)字附加處理器處理器)
文件頁數(shù): 13/28頁
文件大?。?/td> 187K
代理商: SAA7710T
1998 Mar 13
13
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
I
2
C-
BUS FUNCTION BITS
Input selector control register
The write only, two byte, input selector control register is
located on absolute address 0FFFH (4095) and consists
of 16 bits, starting with bit 0 and ending with bit 15.
Deviation from the I
2
C-bus specification
1.
The data hold time (t
HD;DAT
) for this device (
0 ns as
stated in the I
2
C-bus specification) should be as
follows:
a) For the crystal oscillator mode (SHTCB = 0):
f
xtal
b) For the slave oscillator mode (SHTCB = 0):
f
slave
c) For the slave oscillator mode (SHTCB = 1):
slave
--6
-----6
f
During the write cycle, the I
2
C-bus clock frequency must
be reduced.
The I
2
C-bus clock frequency has the following constraints:
f
s
>
2
×
f
IIC
f
s
= I
2
S-bus sampling frequency
f
IIC
= I
2
C-bus clock frequency.
If this constraint cannot be met, a higher I
2
C-bus frequency
can be obtained in the following way:
By making the I
2
C-bus master insert a delay (t
d
) after the
acknowledge pulse (see Fig.11). The delay should be
larger than or equal to 1/f
s
where f
s
is the I
2
S-bus
sampling frequency.
By not using the auto-increment feature. This means
that each data word must be preceded by its intended
destination address.
Fig.11 Timing of reduced I
2
C-bus frequency.
handbook, full pagewidth
MGE756
ACKNOWLEDGE AFTER WORD
td
auto-increment address register
SCL
SDA
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