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參數(shù)資料
| 型號(hào)： | SAA7710T |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | High Quality Audio-Performance Digital Add-On Processor For Digital Sound Systems.(應(yīng)用在數(shù)字聲音系統(tǒng)的高品質(zhì)音頻性能數(shù)字附加處理器) |
| 中文描述： | 高品質(zhì)音頻高性能數(shù)字加到了數(shù)字音響系統(tǒng)。（應(yīng)用在數(shù)字聲音系統(tǒng)的高品質(zhì)音頻性能數(shù)字附加處理器處理器） |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 187K |
| 代理商： | SAA7710T |
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1998 Mar 13
10
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround;
Incredible Sound
SAA7710T
I
2
C-bus control and commands
C
HARACTERISTICS OF THE
I
2
C-
BUS
The I
2
C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to the V
DDX
via a pull-up resistor when
connected to the output stages of a microprocessor.
Data transfer can only be initiated when the bus is not
busy.
B
IT TRANSFER
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals.
The maximum clock frequency is 100 kHz (see Fig.7).
START
AND
STOP
CONDITIONS
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P) (see Fig.8).
D
ATA TRANSFER
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’ (see Fig.9).
A
CKNOWLEDGE
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull
down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse, set up and hold times
must be taken into account. A master receiver must signal
an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of
the slave. In this event the transmitter must leave the data
line HIGH to enable the master to generate a STOP
condition (see Fig.10).
Fig.7 Bit transfer on the I
2
C-bus.
handbook, full pagewidth
MLC160
SDA
SCL
data line
stable
data valid
change
of data
allowed
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| SAA7715AH | Digital Signal Processor |
| SAA7715 | Digital Signal Processor |
| SAA7715H | Digital Signal Processor |
| SAA7740 | Digital Audio Processing IC DAPIC |
| SAA7740H | Digital Audio Processing IC DAPIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7710T/N104 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dolby* Pro Logic Surround; Incredible Sound |
| SAA7712 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Sound effects DSP |
| SAA7712H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Sound effects DSP |
| SAA7715 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Signal Processor |
| SAA7715H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Signal Processor |
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