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參數(shù)資料
| 型號(hào)： | SAA7157T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Clock signal generator circuit for digital TV systems SCGC |
| 中文描述： | 29 MHz, VIDEO CLOCK GENERATOR, PDSO20 |
| 封裝： | PLASTIC, SO-20 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大小： | 80K |
| 代理商： | SAA7157T |
May 1992
7
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
SAA7157
Notes
1.
2.
f
LFCO
= 7.0 MHz and output load 40 pF (Fig.3). V
SSA
and V
SSD
short connected together.
t
comp
is the rise time from LOW of all clocks to HIGH of all clocks (Fig.3) including rise time, skew and jitter
components. Measurements taken between 0.6 V and 2.6 V. Skew between two LLx clocks will not deviate more
than
±
2 ns if output loads are matched within 20%.
MS and LFCO2 functions not tested.
3.
Output signals LL1.5A, LL1.5B, LL3A and LL3B
(pins 7, 10, 14, and 20); note 3
V
OL
V
OH
t
comp
f
LL
output voltage LOW
output voltage HIGH
composite rise time
output frequency LL1.5A
output frequency LL1.5B
output frequency LL3A
output frequency LL3B
rise and fall times
duty factor LL1.5A, LL1.5B, LL3A
and LL3B (mean values)
I
O L
= 2 mA
I
OH
=
0.5 mA
Fig.3; notes 1 and 2
Fig.3
0
2.6
-
-
-
-
-
-
-
-
-
4 f
LFCO(2)
4 f
LFCO(2)
2 f
LFCO(2)
2 f
LFCO(2)
-
0.6
V
DDD
8
V
V
ns
MHz
MHz
MHz
MHz
ns
t
r
, t
f
t
LL
note 1; Fig.3
note 1; Fig.3;
at 1.5 V level
5
43
50
57
%
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Fig.3 Output timing.
handbook, full pagewidth
MEH456
tHD
tHD
tSU
tLL1.5H
tLL1.5L
tLL1.5
2.4 V
0.6 V
2.6 V
1.5 V
0.6 V
2.6 V
1.5 V
0.6 V
tr
tr
tf
tcomp
tf
tLL3L
tLL3H
tLL3
LL3A
LL3B
LL1.5A
LL1.5B
CREF
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