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參數(shù)資料
| 型號： | SAA7157T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Clock signal generator circuit for digital TV systems SCGC |
| 中文描述： | 29 MHz, VIDEO CLOCK GENERATOR, PDSO20 |
| 封裝： | PLASTIC, SO-20 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 80K |
| 代理商： | SAA7157T |
May 1992
4
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
SAA7157
CREF output
TV2 digital clock reference output signal. Clock qualifier signal to TV system with 2 times of LFCO or LFCO2 frequency.
Power-on reset
Power-on reset is activated at power-on, when the supply voltage decreases below 3.5 V (Fig.4) or when chip enable is
done. The indicator output RESN is LOW for a time determined by capacitor on pin 3. The RESN signal can be applied
to reset other circuits of this digital TV system.
The LFCO or LFCO2 input signals have to be applied before RESN becomes HIGH.
PINNING
Note
1.
MS and LFCO2 functions are not tested. LFCO2 is a multiple of horizontal frequency.
SYMBOL
PIN
DESCRIPTION
MS
CE
PORD
V
SSA
V
DDA
V
SSD1
LL1.5A
V
DDD1
V
SSD2
LL1.5B
LFCO
RESN
V
SSD3
LL3A
CREF
LFCOSEL
V
DDD2
V
SSD4
LFCO2
LL3B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
mode select input (LOW = PLL mode)
chip enable /reset (HIGH = outputs enabled)
power-on reset delay, dependent on external capacitor
analog ground (0 V)
analog supply voltage (
+
5 V)
digital ground 1 (0 V)
line-locked clock output signal 1.5A (4 times f
LFCO
)
digital supply voltage 1 (
+
5 V)
digital ground 2 (0 V)
line-locked clock output signal 1.5B (4 times f
LFCO
)
line-locked frequency control input signal 1
reset output (active-LOW, Fig.4)
digital ground 3 (0 V)
line-locked clock output signal 3A (2 times f
LFCO
)
clock reference output, qualifier signal (2 times f
LFCO
)
LFCO source select (LOW = LFCO selected)
(1)
digital supply voltage 2 (
+
5 V)
digital ground 4 (0 V)
line-locked frequency control input signal 2
(1)
line-locked clock output signal 3B (2 times f
LFCO
)
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