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參數(shù)資料
| 型號： | SAA7157T |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Clock signal generator circuit for digital TV systems SCGC |
| 中文描述： | 29 MHz, VIDEO CLOCK GENERATOR, PDSO20 |
| 封裝： | PLASTIC, SO-20 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 80K |
| 代理商： | SAA7157T |
May 1992
6
Philips Semiconductors
Product specification
Clock signal generator circuit for digital TV
systems (SCGC)
SAA7157
CHARACTERISTICS
V
DDA
= 4.5 to 5.5 V; V
DDD
= 4.5 to 5.5 V; f
LFCO
= 6.0 to 7.25 MHz and T
amb
= 0 to 70
°
C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DDA
V
DDD
I
DDA
I
DDD
V
reset
analog supply voltage (pin 5)
digital supply voltage (pins 8 and 17)
analog supply current (pin 5)
digital supply current (I
8
+
I
17
)
power-on reset threshold voltage
4.5
4.5
3
10
5.0
5.0
3.5
5.5
5.5
9
60
V
V
mA
mA
V
note 1
Fig.4
Input LFCO
(pin 11)
V
11
V
i
f
LFCO
C
11
DC input voltage
input signal (peak-to-peak value)
input frequency range
input capacitance
0
1
6.0
V
DDA
V
DDA
7.25
10
V
V
MHz
pF
Inputs MS, CE, LFCOSEL and LFCO2
(pins 1, 2, 16 and 19); note 3
V
IL
V
IH
f
LFCO2
I
LI
input voltage LOW
input voltage HIGH
input frequency range for LFCO2
input leakage current
0
2.0
6.0
50
0.8
V
DDD
7.25
150
10
5
V
V
MHz
μ
A
μ
A
pF
LFCOSEL
others
C
I
input capacitance
Output RESN
(pin 12)
V
OL
V
OH
t
d
output voltage LOW
output voltage HIGH
RESN delay time
I
O L
= 2 mA
I
OH
=
0.5 mA
C
3
= 0.1
μ
F; Fig.4
0
2.4
20
0.4
V
DDD
200
V
V
ms
Output CREF
(pin 15)
V
OL
V
OH
f
CREF
C
L
t
SU
t
HD
output voltage LOW
output voltage HIGH
output frequency CREF
output load capacitance
set-up time
hold time
I
O L
= 2 mA
I
OH
=
0.5 mA
Fig.3
0
2.4
15
12
4
2 f
LFCO(2)
0.6
V
DDD
V
V
MHz
pF
ns
ns
40
Fig.3; note 1
Fig.3; note 1
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