參數(shù)資料
型號(hào)： SAA7130
廠商： NXP Semiconductors N.V.
英文描述： PCI video broadcast decoder
中文描述： PCI視頻廣播解碼器
文件頁(yè)數(shù)： 33/48頁(yè)
文件大?。?/td> 196K
代理商： SAA7130
2002 Apr 23
33
Philips Semiconductors
Product specification
PCI video broadcast decoder
SAA7130HL
7.8
DTV/DVB channel decoding and TS capture
The SAA7130HL is optimum equipped to support the
application extension to capture digital TV signals, e.g. for
VSB (ATSC) or DVB (T/C/S). A hybrid TV tuner for analog
and digital TV broadcast reception usually provides a DTV
signal on low IF, i.e. downconverted into a frequency
range from 0 to 10 MHz. Such signals can be fed to one of
the 5 video inputs of the SAA7130HL for digitizing. The
digital raw DTV is output at the video port, and is sent to
the peripheral channel decoder, e.g. TDA8961 for VSB-8
decoding. The channel decoder provides the sampling
clock via the external clock input pin X_CLK_IN (up to
36 MHz input clock frequency), and adjusts the signal gain
in the tuner or in the video input path in front of the ADC.
Alternatively, the low IF DTV/DVB signal could be fed
directly to the channel decoder, depending on the
capability for digitizing the selected device.
The peripheral channel decoder circuitry decodes the
digital transmission into bits and bytes, apply error
correction etc., and outputs a packed Transport Stream
(TS) accompanied by a clock and handshake signals. The
SAA7130HL captures the TS in parallel or serial protocol,
synchronized by Start Of Packet (SOP), and pumps it via
the dedicated DMA into the PCI memory space. The DMA
definition supports automatic toggling between two
buffers.
7.9
Control of peripheral devices
7.9.1
I
2
C-
BUS MASTER
The SAA7130HL incorporates an I
2
C-bus master to set-up
and control peripheral devices such as tuner, DTV/DVB
channel decoder, audio DSP co-processors, etc. The
I
2
C-bus interface itself is controlled from the PCI-bus on a
command level, reading and writing byte by byte. The
actual I
2
C-bus status is reported (status register) and, as
an option, can raise error interrupts on the PCI-bus.
At PCI reset time, the I
2
C-bus master receives board
specific information from the on-board EEPROM to update
the PCI configuration registers.
The I
2
C-bus interface is multi-master capable and can
assume slave operation too. This allows application of the
device in the stand-alone mode, i.e. with the PCI-bus not
connected. Under the slave mode, all internal
programming registers can be reached via the I
2
C-bus
with exception of the PCI configuration space.
7.9.2
P
ROPAGATE RESET
The PCI system reset and ACPI power management
state D3 is propagated to peripheral devices by the
dedicated pin PROP_RST. This signal is switched to
active LOW by reset and D3, and is only switched HIGH
under control of the device driver ‘by will’. The intention is
that peripheral devices will use signal PROP_RST as
Chip-Enable (CE). The peripheral devices should enter a
low power consumption state if pin PROP_RST = LOW,
and reset into default setting at the rising edge.
7.9.3
GPIO
The SAA7130HL offers a set of General Purpose
Input/Output (GPIO) pins, to interface to on-board
peripheral circuits. These GPIOs are intended to take over
dedicated functions:
Digital video port output: 8-bit or 16-bit wide (including
raw DTV)
Transportstreaminput:parallelorserial(alsoapplicable
as I
2
S-bus input)
Peripheral interrupt input: four GPIO pins of the
SAA7130HL can be enabled to raise an interrupt on the
PCI-bus. By this means, peripheral devices can directly
intercept with the device driver on changed status or
error conditions.
Any GPIO pin that is not used for a dedicated function is
available for direct read and write access via the PCI-bus.
Any GPIO pin can be selected individually as input or
output (masked write). By these means, very tailored
interfacing to peripheral devices can be created via the
SAA7130HL capture driver running on Windows operating
systems.
At system reset (PCI reset) all GPIO pins will be set to
3-state and input, and the logic level present on the GPIO
pins at that moment will be saved into a special ‘strap’
register. All GPIO pins have an internal pull-down resistor
(LOW level), but can be strapped externally with a 4.7 k
resistor to the supply voltage (HIGH level). The device
driver can investigate the strap register for information
about the hardware configuration of a given board.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA7130HL 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:PCI video broadcast decoder
SAA7130HL/V1,518 功能描述:視頻 IC PCI 9-BIT VID DECODR RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
SAA7130HL/V1,557 功能描述:視頻 IC PCI 9-BIT VID DECODR RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
SAA7130HLBE 功能描述:視頻 IC PCI 9-BIT VID DECODR RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
SAA7130HLBE-T 功能描述:視頻 IC PCI 9-BIT VID DECODR RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
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