參數(shù)資料
型號: SAA6752HS
廠商: NXP Semiconductors N.V.
英文描述: MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
中文描述: MPEG - 2視頻和MPEG-audio/AC-3音頻編碼器與復用器
文件頁數(shù): 9/71頁
文件大小: 2570K
代理商: SAA6752HS
2004 Jan 26
9
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3
audio encoder with multiplexer
SAA6752HS
PDO1
PDO2
V
DDP
PDO3
PDO4
PDO5
PDO6
V
SSP
PDO7
PDIOCLK
I2CADDRSEL
SD_DQ15
V
DDP
SD_DQ0
SD_DQ14
SD_DQ1
V
SSP
SD_DQ13
SD_DQ2
SD_DQ12
V
DDP
SD_DQ3
SD_DQ11
SD_DQ4
SD_DQ10
V
SSP
SD_DQ5
SD_DQ9
SD_DQ6
SD_DQ8
V
DDP
SD_DQ7
SD_DQM1
SD_DQM0
SD_WE
V
SSP
SD_CAS
SD_CLK
SD_RAS
SD_CKE
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
3-state output
3-state output
supply
3-state output
3-state output
3-state output
3-state output
ground
3-state output
input/output
input
input/output
supply
input/output
input/output
input/output
ground
input/output
input/output
input/output
supply
input/output
input/output
input/output
input/output
ground
input/output
input/output
input/output
input/output
supply
input/output
output
output
output
ground
output
output
output
output
4
4
4
4
4
4
4
4
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
parallel stream data output bit 1
parallel stream data output bit 2
pad ring supply voltage (3.3 V)
parallel stream data output bit 3
parallel stream data output bit 4
parallel stream data output bit 5
parallel stream data output bit 6
pad ground
parallel stream data output bit 7 (MSB)
parallel stream clock input/output
I
2
C-bus address select input with internal pull-up resistor
SDRAM data input/output bit 15 (MSB)
pad ring supply voltage (3.3 V)
SDRAM data input/output bit 0 (LSB)
SDRAM data input/output bit 14
SDRAM data input/output bit 1
pad ground
SDRAM data input/output bit 13
SDRAM data input/output bit 2
SDRAM data input/output bit 12
pad ring supply voltage (3.3 V)
SDRAM data input/output bit 3
SDRAM data input/output bit 11
SDRAM data input/output bit 4
SDRAM data input/output bit 10
pad ground
SDRAM data input/output bit 5
SDRAM data input/output bit 9
SDRAM data input/output bit 6
SDRAM data input/output bit 8
pad ring supply voltage (3.3 V)
SDRAM data input/output bit 7
SDRAM data mask enable output bit 1
SDRAM data mask enable output bit 0 (LSB)
SDRAM write enable output (active LOW)
pad ground
SDRAM column address strobe output (active LOW)
SDRAM clock output
SDRAM row address strobe output (active LOW)
SDRAM clock enable output
SYMBOL
PIN
INPUT/OUTPUT
(1)
I
max
(mA)
DESCRIPTION
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