參數(shù)資料
型號: SAA6752HS
廠商: NXP Semiconductors N.V.
英文描述: MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
中文描述: MPEG - 2視頻和MPEG-audio/AC-3音頻編碼器與復(fù)用器
文件頁數(shù): 23/71頁
文件大?。?/td> 2570K
代理商: SAA6752HS
2004 Jan 26
23
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3
audio encoder with multiplexer
SAA6752HS
7.4
Digital audio input
7.4.1
G
ENERAL
The audio input interface (I
2
S) accepts serial digital audio
data and supports master and slave mode. The interface
is able to handle 16 to 20 bits audio data with left and right
channel. Audio data with more than 20-bit word width is
accepted as input, but the additional bits are ignored.
7.4.2
A
UDIO PORT CONFIGURATION OPTIONS
The following configuration options can be selected from
the host:
AUDIO INPUT PORT SELECTION. Two digital audio
input ports are selectable.
AUDIO INPUT FORMAT. Various I
2
S and EIAJ formats
can be selected.
AUDIO INPUT MODES. Master or slave mode can be
selected.
AUDIO CLOCK OUTPUT. An audio clock output
(256
×
48 kHzor384
×
48 kHz)canbeusedforexternal
analog-to-digital converter clocking.
AUDIO OUTPUT. The second audio interface port can
be configured as output in special applications e.g.
concurrent encoding of audio and video without internal
multiplexing of the two streams.
7.4.3
I
NPUT FORMATS
The digital audio input interface can select between two
digital audio input ports via I
2
C-bus control and is able to
input the following audio formats:
I
2
S, see Fig.5
EIAJ, see Fig.6
EIAJ alternative format.
The alternative formats are defined as having the word
select shifted by one clock cycle with respect to the data.
EIAJ and EIAJ alternative format are supported for 16, 18
and 20-bit resolution. I
2
S and I
2
S alternative format are
supported for 16, 18, 20 and 24-bit resolution. Input data is
truncated to 20 bits internally if 24-bit resolution is applied.
Each of the formats can be applied in master or slave
mode.
When in master mode, the external audio analog-to-digital
convertor must be clocked using the audio clock
generated by the SAA6752HS. This can be set to
256
×
48 kHz or 384
×
48 kHz.
In slave mode an internal sample rate converter converts
theinput samplefrequencytoa videoframelocked48 kHz
sample frequency.
If video is not present and/or the clock mode is set to
mode 3, the audio clock frequency is locked to the fixed
nominal system frequency (crystal or external). In all other
cases the audio clock will be locked to the video frame
frequency.
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