參數(shù)資料
型號: SAA6752HS
廠商: NXP Semiconductors N.V.
英文描述: MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer
中文描述: MPEG - 2視頻和MPEG-audio/AC-3音頻編碼器與復(fù)用器
文件頁數(shù): 65/71頁
文件大?。?/td> 2570K
代理商: SAA6752HS
2004 Jan 26
65
Philips Semiconductors
Product specification
MPEG-2 video and MPEG-audio/AC-3
audio encoder with multiplexer
SAA6752HS
Notes
1.
2.
3.
Short-circuit current is only allowed for a short time (<1 s).
The output pins are 3.3 V tolerant when in 3-state mode.
Pins SCL and SDA of the I
2
C-bus interface do not obstruct the SDA and SCL lines if the supply voltage V
DDP
is
switched off.
The open-drain outputs are 3.3 V tolerant.
Frame-locked input data rate deviation from SAA6752HS crystal clock.
Supporting output range of the Philips SAA7114 video input processor.
Applies for line frequencies
±
2% from nominal.
Minimum limit according to IEC 60756; maximum limit because the SAA6752HS may drop frames for V-sync
frequencies greater than 1.5% above nominal.
Deviation according to IEC 60756.7. The SAA6752HS will only encode 240 lines (when in 525-line mode) and
288 lines (when in 625-line mode). Therefore any additional lines in a field above these values will not be encoded.
10. Pin XTALO has to be used for connection with a crystal only. Do not use for other purposes.
11. The required stability of the crystal frequency or external system clock is dependent upon the clock mode used in the
application.
4.
5.
6.
7.
8.
9.
handbook, full pagewidth
MHC142
valid
not valid
valid
1.7 V
0.7 V
1.7 V
1.3 V
0.7 V
data and
control
inputs
VCLK
Tcy
tLOW
tHIGH
valid
not valid
valid
2.4 V
0.4 V
data and
control
outputs
tf(VCLK)
tHD;DAT
tr(VCLK)
tSU;DAT
tOH;DAT
Fig.15 Clock data timing.
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