參數(shù)資料
型號(hào)： SAA6721
廠商： NXP Semiconductors N.V.
英文描述： SXGA RGB to TFT graphics engine
中文描述： SXGA RGB到液晶圖形引擎
文件頁(yè)數(shù)： 62/72頁(yè)
文件大小： 360K
代理商： SAA6721
1999 May 11
62
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
11 TIMING CHARACTERISTICS
V
DDD
= 3.0 to 3.6 V; V
DD(PLL)
= 3.1 to 3.5 V; T
amb
= 25
°
C; see Fig.23; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock input at pin CLK
f
CLK
δ
clock frequency
duty factor
24
40
50
70
60
MHz
%
RGB/YUV sample clock input at pin VCLK
f
VCLK
clock frequency
single ADC mode
double ADC mode
25
12.5
40
50
150
75
60
MHz
MHz
%
δ
duty factor
Input signals at pins VVS, VHS, VPA7 to VPA0, VPB7 to VPB0, VPC7 to VPC0, VPD7 to VPD0, VPE7 to VPE0,
and VPF7 to VPF0 with respect to signal at pin VCLK
t
su
t
h
set-up time
hold time
4.0
7.0
ns
ns
Output signals at pins CLAMP and GAINC with respect to signal at pin VCLK;
note 1
t
h
t
PD
hold time
propagation delay
8
13
ns
ns
Output clock to panel at pin PCLK
f
PCLK
δ
clock frequency
duty factor
40
50
80
60
MHz
%
Output signals at pins PVS, PHS, PDE, PAR7 to PAR0, PAG7 to PAG0, PAB7 to PAB0, PBR7 to PBR0,
PBG7 to PBG0, and PBB7 to PBB0 with respect to signal at pin PCLK;
note 2
t
h
hold time
pins PVS, PHS and PDE
all other pins
propagation delay
pins PVS, PHS and PDE
all other pins
0.5
0
ns
ns
t
PD
1
3.5
ns
ns
Overlay port clock output at pin OVCLK
f
OVCLK
δ
clock frequency
duty factor
80
60
MHz
%
40
50
Input signals at pins OVACT, OVA2 to OVA0, and OVB2 to OVB0 with respect to signal at pin OVCLK
t
su(i)
t
h(i)
set-up time
hold time
6.0
3.0
ns
ns
Output signals at pins OVVS and OVHS with respect to signal at pin OVCLK;
note 1
t
h(o)
t
PD(o)
hold time
propagation delay
1.0
1.0
ns
ns
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