參數(shù)資料
型號(hào): SAA6721
廠商: NXP Semiconductors N.V.
英文描述: SXGA RGB to TFT graphics engine
中文描述: SXGA RGB到液晶圖形引擎
文件頁(yè)數(shù): 33/72頁(yè)
文件大小: 360K
代理商: SAA6721
1999 May 11
33
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
I
NTERLACED MODE PROGRAMMING
YUV CREF polarity
YUV clock qualifier is active LOW
YUV clock qualifier is active HIGH
YUV HREF polarity
Active data qualifier is active LOW
Active data qualifier is active HIGH
YUV format
CCIR 656
4 : 1 : 1 format
4 : 2 : 2 format
4 : 4 : 4 format
YUV field sampling mode
All incoming frames are captured
Capture alternating fields only
Capture odd fields only
Capture even fields only
Field reverse flag
Keep original odd field identification
Change field identification
34
W
D0
logic 0
logic 1
D1
logic 0
logic 1
D3 and D2
D3 = 0 and D2 = 0
D3 = 0 and D2 = 1
D3 = 1 and D2 = 0
D3 = 1 and D2 = 1
D5 and D4
D5 = 0 and D4 = 0
D5 = 0 and D4 = 1
D5 = 1 and D4 = 0
D5 = 1 and D4 = 1
D6
logic 0
logic 1
V
ERTICAL SAMPLE OFFSET
Vertical sample offset from Vsync
35 and 36
W
D10 to D0
H
ORIZONTAL SAMPLE OFFSET
Horizontal sample offset from Hsync
37 and 38
W
D11 to D0
V
ERTICAL SAMPLE LENGTH
Vertical sample window length
39 and 40
W
D10 to D0
H
ORIZONTAL SAMPLE LENGTH
Horizontal sample window length
41 and 42
W
D11 to D0
C
LAMP PULSE START
Start of clamp pulse after active edge of Hsync
43
W
D7 to D0
C
LAMP PULSE END
End of clamp pulse after active edge of Hsync
44
W
D7 to D0
G
AIN CORRECTION PULSE START DELAY
Delay of start of GAINC pulse from first edge of Hsync
45
W
D7 to D0
G
AIN CORRECTION PULSE END DELAY
Delay of end of pulse GAINC from second edge of Hsync
46
W
D7 to D0
NAME
SUBADDRESS
R/W
DATA
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