- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372112 > SAA6721 (NXP Semiconductors N.V.) SXGA RGB to TFT graphics engine PDF資料下載
參數(shù)資料
| 型號： | SAA6721 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | SXGA RGB to TFT graphics engine |
| 中文描述： | SXGA RGB到液晶圖形引擎 |
| 文件頁數(shù)： | 38/72頁 |
| 文件大?。?/td> | 360K |
| 代理商： | SAA6721 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當(dāng)前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
1999 May 11
38
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
OSD overlay port
G
ENERAL CONFIGURATION
OSD overlay port activation
Overlay information will not be inserted into data stream
Overlay information will be inserted into data stream
Sync pulse generation
No sync pulses will be generated
Sync pulses will be generated
Clock edge for sampling
Data sampling at falling edge of clock at pin OVCLK
Data sampling at rising edge of clock at pin OVCLK
Clock gating
OVCLK always enabled
OVCLK enabled only during internal active video processing
Horizontal sync polarity
Active LOW horizontal sync pulse at pin OVHS
Active HIGH horizontal sync pulse at pin OVHS
Vertical sync polarity
Active LOW vertical sync pulse at pin OVVS
Active HIGH vertical sync pulse at pin OVVS
Overlay port active pixel qualifier polarity
Active LOW qualifier signal at pin OVACT
Active HIGH qualifier signal at pin OVACT
Overlay port clock polarity
Sync pulse change with respect to falling edge at pin OVCLK
Sync pulse change with respect to rising edge at pin OVCLK
99
W
D0
logic 0
logic 1
D1
logic 0
logic 1
D2
logic 0
logic 1
D3
logic 0
logic 1
D4
logic 0
logic 1
D5
logic 0
logic 1
D6
logic 0
logic 1
D7
logic 0
logic 1
O
VERLAY HORIZONTAL SYNC START
Start of horizontal sync pulse with respect to left frame border
100 and 101
W
D10 to D0
O
VERLAY HORIZONTAL SYNC LENGTH
Length of horizontal sync pulse
102 and 103
W
D10 to D0
O
VERLAY HORIZONTAL SYNC LATENCY
Delay between start of horizontal sync and valid overlay data
104
W
D7 to D0
O
VERLAY WINDOW HORIZONTAL LENGTH
Horizontal length of overlay region
105 and 106
W
D10 to D0
O
VERLAY WINDOW VERTICAL OFFSET
Vertical offset of overlay region
107 and 108
W
D10 to D0
O
VERLAY WINDOW VERTICAL LENGTH
Vertical length of overlay region
109 and 110
W
D10 to D0
NAME
SUBADDRESS
R/W
DATA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA6721E | SXGA RGB to TFT graphics engine(XGA RGB 到 TFT圖形引擎) |
| SAA6750 | Encoder for MPEG2 image recording EMPIRE |
| SAA6750H | Encoder for MPEG2 image recording EMPIRE |
| SAA6752HS | MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
| SAA7102 | Circular Connector; MIL SPEC:MIL-C-5015; Body Material:Metal; Series:GT; No. of Contacts:12; Connector Shell Size:28; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA6721E | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:SXGA RGB to TFT graphics engine |
| SAA6750 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE |
| SAA6750H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Encoder for MPEG2 image recording EMPIRE |
| SAA6752HS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
| SAA6752HS/V103 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 video and MPEG-audio/AC-3 audio encoder with multiplexer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。