- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98072 > SAA5532PS/NNNN (NXP SEMICONDUCTORS) 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP52 PDF資料下載
參數(shù)資料
| 型號(hào)： | SAA5532PS/NNNN |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP52 |
| 封裝： | 0.600 INCH, PLASTIC, SDIP-52 |
| 文件頁(yè)數(shù)： | 41/100頁(yè) |
| 文件大?。?/td> | 412K |
| 代理商： | SAA5532PS/NNNN |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)當(dāng)前第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)
2000 Feb 23
45
Philips Semiconductors
Preliminary specication
Enhanced TV microcontrollers with
On-Screen Display (OSD)
SAA55xx
18.1.1
CVBS SWITCH
The CVBS switch is used to select the required analog
input depending on the value of TXT8.CVBS1/CVBS0.
18.1.2
ANALOG-TO-DIGITAL CONVERTER
The output of the CVBS switch is passed to a
Differential-to-Single-Ended Converter (DIVIS), although
in this device it is used in single-ended configuration with
a reference. The analog output of the DIVIS is converted
into a digital representation by a full-flash ADC with a
sampling rate of 12 MHz.
18.1.3
MULTI-RATE VIDEO INPUT PROCESSOR
The multi-rate video input processor is a Digital Signal
Processor designed to extract the data and recover the
clock from a digitized CVBS signal.
18.1.4
DATA STANDARDS
The data and clock standards that can be recovered are
shown in Table 13.
Table 13 Data Slicing standards
18.1.5
DATA CAPTURE TIMING
The Data Capture timing section uses the synchronisation
information extracted from the CVBS signal to generate
the required horizontal and vertical reference timings.
The timing section automatically recognizes and selects
the appropriate timings for either 625 (50 Hz)
synchronisation or 525 (60 Hz) synchronisation.
A flag TXT12.VIDEO SIGNAL QUALITY is set when the
timing section is locked correctly to the incoming CVBS
signal. When TXT12.VIDEO SIGNAL QUALITY is set
another flag TXT12.525/625 SYNC can be used to identify
the standard.
18.1.6
ACQUISITION
The acquisition sections extracts the relevant information
from the serial stream of data from the MulVIP and stores
it in memory.
18.1.6.1
Making a page request
A page is requested by writing a series of bytes into the
TXT3.PRD<4:0> SFR which corresponds to the number of
the page required. The bytes written into TXT3 are stored
in a RAM with an auto-incrementing address. The start
address for the RAM is set using the TXT2.SC<2:0> to
define which part of the page request is being written, and
TXT2.REQ<3:0> is used to define which of the 10 page
requests is being modified. If TXT2.REQ<3:0> is greater
than 09H, then data being written to TXT3 is ignored.
Table 14 shows the contents of the page request RAM.
Up to 10 pages of teletext can be acquired on the 10 page
device, when TXT1.EXT PKT OFF is set to logic 1, and up
to 9 pages can be acquired when this bit is set to logic 0.
For a 20 page device the 10 page acquisition channels are
banked, the bank being selected using TXT2.ACQ BANK.
If the ‘Do Care’ bit for part of the page number is set logic 0
then that part of the page number is ignored when the
teletext decoder is deciding whether a page being
received off air should be stored or not. For example, if the
Do Care bits for the four subcode digits are all set to logic 0
then every subcode version of the page will be captured.
Table 14 The contents of the Page request RAM
DATA STANDARD
CLOCK RATE
625 WST
6.9375 MHz
525 WST
5.7272 MHz
VPS
5.0 MHz
WSS
5.0 MHz
Closed Caption
500 kHz
START
COLUMN
PRD4
PRD3
PRD2
PRD1
PRD0
0
DO CARE
Magazine
HOLD MAG2 MAG1 MAG0
1
DO CARE
Page Tens
PT3
PT2
PT1
PT0
2
DO CARE
Page
Units
PU3
PU2
PU1
PU0
3
DO CARE
Hour Tens
X
HT1
HT0
4
DO CARE
Hours
Units
HU3
HU2
HU1
HU0
5
DO CARE
Minutes
Tens
X
MT2
MT1
MT0
6
DO CARE
Minutes
Units
MU3
MU2
MU1
MU0
7
X
XXE1
E0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA5551PS/NNNN | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP52 |
| SAA5500PS/NNNN | 8-BIT, OTPROM, 12 MHz, MICROCONTROLLER, PDIP52 |
| SAA6703AH | CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160 |
| SAA7157T-T | 29 MHz, VIDEO CLOCK GENERATOR, PDSO20 |
| SAA7388GP-T | 8-BIT, 50.4 MHz, MICROCONTROLLER, PQFP80 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA5533 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced TV microcontrollers with On-Screen Display OSD |
| SAA5533PS | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced TV microcontrollers with On-Screen Display OSD |
| SAA5540PS/NNNN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) |
| SAA5541PS/NNNN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) |
| SAA5542 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced TV microcontrollers with On-Screen Display OSD |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。