參數(shù)資料
型號(hào): SAA5281
廠商: NXP Semiconductors N.V.
英文描述: Integrated Video input processor and Teletext decoder IVT1.8
中文描述: 集成視頻輸入處理器和圖文電視解碼器IVT1.8
文件頁(yè)數(shù): 25/48頁(yè)
文件大?。?/td> 1187K
代理商: SAA5281
1996 Nov 04
25
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Table 11
Register map for page requests (R3); notes 1 to 6
Notes
1.
2.
Abbreviations are as given in Table 6 except for DO CARE bits and CH = chapter address for acquisition chapter.
When the DO CARE bit is set to logic 1 this means the corresponding digit is to be taken into account for page
requests. If the DO CARE bit is set to logic 0 the digit is ignored. This allows, for example, normal or timed page
selection.
If HOLD is set LOW, the page is held and not updated.
Columns auto-increment on successive I
2
C-bus transmission bytes.
The SUBTITLE bit is only present when the device is in ‘1.8 mode’ (i.e. R13D6 has been set HIGH).
X = don’t care.
3.
4.
5.
6.
Table 12
Acquisition channel programming
Note
1.
These register bits operate in conjunction with 7 + P/ 8-BIT (Register 1, Bit D6) which will over-ride the choice of data
checker if set, setting all channels to 8-bit only. If this bit is not set H0 to H3 and S0 to S3 will determine the data
checking (default to 7-bit + parity).
START
COLUMN
PRD4
PRD3
PRD2
PRD1
PRD0
0
DO CARE
Magazine
DO CARE
Page tens
DO CARE
Page units
DO CARE
Hours tens
DO CARE
Hours units
DO CARE
Minutes tens
DO CARE
Minutes units
X
HOLD
MAG2
MAG1
MAG0
1
PT3
PT2
PT1
PT0
2
PU3
PU2
PU1
PU0
3
SUBTITLE
X
HT1
HT0
4
HU3
HU2
HU1
HU0
5
X
MT2
MT1
MT0
6
MU3
X
MU2
CH2
MU1
CH1
MU0
CH0
7
H0 to H3
(1)
S0 to S3
(1)
CHECKING ALGORITHM FOR ACQUISITION CHANNEL X
0
0
1
0
1
0
7-bit + parity for whole page
8-bit for whole page
8/4 Hamming check for whole page
mixed 8/4 Hamming (columns 0 to 7, 20 to 27) and 7-bit + parity
(columns 8 to 19, 28 to 39)
1
1
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