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參數(shù)資料
| 型號(hào)： | SAA5281 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Integrated Video input processor and Teletext decoder IVT1.8 |
| 中文描述： | 集成視頻輸入處理器和圖文電視解碼器IVT1.8 |
| 文件頁數(shù)： | 23/48頁 |
| 文件大?。?/td> | 1187K |
| 代理商： | SAA5281 |
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1996 Nov 04
23
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
R4 DISPLAY CHAPTER - auto-increments to Register 5
A0 to A2
FREEZE HEADER ONLY
Selects one of 8 display chapters.
Freezes the rolling header, but (unlike R0D4) allows the time to roll.
R5 NORMAL DISPLAY CONTROL - auto-increments to Register 6
R6 NEWSFLASH/SUBTITLE DISPLAY CONTROL - auto-increments to Register 7;
note 1
PON
TEXT
COR
BKGND
Picture on.
Text on.
Contrast reduction on.
Background colour on.
R7 DISPLAY MODE - does not auto-increment
BOX ON 0
BOX ON 1 to 23
BOX ON 24
SINGLE/DOUBLE HEIGHT
TOP/BTM HALF
CONCEAL/REVEAL ON
CURSOR ON
STATUS BTM/TOP
Boxing function allowed on Row 0.
Boxing function allowed on Rows1 to 23.
Boxing function allowed on Row 24.
To display double height text.
To select bottom half of page when DOUBLE HEIGHT is logic 1.
To reveal concealed text.
To display cursor.
Row 25 displayed above or below the main text.
R8 ACTIVE CHAPTER - auto-increments to Register 9
A0 to A2
CLEAR MEM
VPS ENABLE
Active chapter for data written to or read from memory via the I
2
C-bus.
When set to logic 1, clears the display memory. This bit is automatically reset.
VPS acquisition enabled when logic 1.
R9 CURSOR ROW - auto-increments to Register 10
R0 to R4
Active row for data written to or read from memory via the I
2
C-bus.
R10 CURSOR COLUMN - auto-increments to Register 11 or 11B
C0 to C5
Active column for data written to or read from memory via the I
2
C-bus.
R11 CURSOR DATA - does not auto-increment
D0 to D7
Data read from/written to memory via I
2
C-bus, at location pointed to by R9 and
R10. This location automatically increments each time R11 is accessed.
R11B DEVICE STATUS - does not auto-increment
VCS SIGNAL QUALITY
Indicates that the video signal quality is good and PLL is phase-locked to input
video when logic 1.
If a good teletext signal is being received then logic 1.
Indicated language/ROM variant. For Western European is logic 0. R3 and R4 are
set HIGH if R13 D6 is logic 1.
If the input video is a 525 line signal then logic 1.
TEXT SIGNAL QUALITY
ROM VER R0 to R4
625/525 SYNC
R12 ADVANCED CONTROL 2A - does not auto-increment
S0 to S3, H0 to H3
Each acquisition channel can be programmed to process its page in one of four
ways as shown in Table 12.
REGISTER BIT D0 TO D7
FUNCTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA5281GP | RES 11.3K OHM 1/16W .5% 0603 SMD |
| SAA5281P | Integrated Video input processor and Teletext decoder IVT1.8 |
| SAA5281ZP | Integrated Video input processor and Teletext decoder IVT1.8 |
| SAA5284GP | Multimedia video data acquisition circuit |
| SAA5284 | Multimedia video data acquisition circuit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA5281GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated Video input processor and Teletext decoder IVT1.8 |
| SAA5281P | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated Video input processor and Teletext decoder IVT1.8 |
| SAA5281ZP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated Video input processor and Teletext decoder IVT1.8 |
| SAA5284 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multimedia video data acquisition circuit |
| SAA5284GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multimedia video data acquisition circuit |
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