參數(shù)資料
型號(hào)： SAA5281
廠商： NXP Semiconductors N.V.
英文描述： Integrated Video input processor and Teletext decoder IVT1.8
中文描述： 集成視頻輸入處理器和圖文電視解碼器IVT1.8
文件頁(yè)數(shù)： 24/48頁(yè)
文件大?。?/td> 1187K
代理商： SAA5281
1996 Nov 04
24
Philips Semiconductors
Preliminary specification
Integrated Video input processor and
Teletext decoder (IVT1.8*)
SAA5281
Note
1.
These functions have IN and OUT referring to inside and outside the boxing function respectively.
Table 9
ODD/EVEN selection
Table 10
Interlace/non-interlace 312/313 line control and ODD/EVEN field detection option
Notes
1.
2.
X = don't care.
Reverts to interlaced mode if a newsflash or subtitle is being displayed.
R13 ADVANCED CONTROL 2B - does not auto-increment
AUTO DISPLAY PKT X/24
Status row will show the contents of the row of the extension memory (packet 24)
when logic 1.
Output taken from processing engine written to the display memory when logic 0.
Operates independent of the acquisition.
When logic 1 all packet 26 data is stored in extension memory unchecked.
Enable for acquisition pointers when logic 1.
VPS acquisition enabled when logic 1.
Enables meshing display function in box mode.
When logic 1, cursor position not updated even if active row and column change.
This bit will also cause R3 and R4 of the ROM code in Register R11B to be set
HIGH. This allows software to identify the device as an IVT1.8*. An internal ‘1.8
mode’ flag is also set, which enables the operation of R0D4, R4D4 and the subtitle
bit in R3.
When logic 1, extension packet data is mapped into the last chapter. Only packet
24, 27/0 and 8/30 are stored. Chapters 0 to 6 can then be used for page storage. If
extension packets are not enabled, 8 pages are stored as normal, but X/26 engine
is enabled.
DISABLE PKT X/26
HAM CHECK 24 : 18
POINTS ENABLE
VPS ENABLE
MESHING ENABLE
CURSOR FREEZE/
DEVICE IDENT
ENHANC MODE
AUTO
ODD/EVEN
DISABLE
ODD/EVEN
RESULT
0
0
1
1
0
1
1
1
ODD/EVEN output continuous
ODD/EVEN statically LOW
ODD/EVEN active only when no TV picture displayed
DV output to indicate reception of error-free 8/30/format 2 packet or VPS line
TCS ON
FFB MODE
(1)
T1
T0
RESULT
X
X
X
0
1
0
0
1
1
1
0
1
0
1
1
interlaced 312.5/312.5 lines
non-interlaced 312/313 lines (note 2)
non-interlaced 312/313 lines (note 2)
SCS (scan composite sync) mode: FFB leading edge in first broad pulse of field
SCS (scan composite sync) mode: FFB leading edge in second broad pulse of field
REGISTER BIT D0 TO D7
FUNCTION
相關(guān)PDF資料
PDF描述
SAA5281GP RES 11.3K OHM 1/16W .5% 0603 SMD
SAA5281P Integrated Video input processor and Teletext decoder IVT1.8
SAA5281ZP Integrated Video input processor and Teletext decoder IVT1.8
SAA5284GP Multimedia video data acquisition circuit
SAA5284 Multimedia video data acquisition circuit
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA5281GP 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Integrated Video input processor and Teletext decoder IVT1.8
SAA5281P 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Integrated Video input processor and Teletext decoder IVT1.8
SAA5281ZP 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Integrated Video input processor and Teletext decoder IVT1.8
SAA5284 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Multimedia video data acquisition circuit
SAA5284GP 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Multimedia video data acquisition circuit
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